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| Presentation | 2014-11-26 11:10 Technology Mapping Method for Low Power Consumption and High Performance in General-Synchronous Framework Junki Kawaguchi, Yukihide Kohira (Univ. of Aizu)  VLD2014-83 DC2014-37 |
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| Abstract | (in Japanese) | (See Japanese page) |
| (in English) | In general-synchronous framework, in which the clock is distributed periodically to each register but not necessarily simultaneously, circuit performances are expected to be improved compared to complete-synchronous framework, in which the clock is distributed periodically and simultaneously to each register. To improve the circuit performances more, logic circuit synthesis for general-synchronous framework is required. In this paper, under the assumption that any clock schedule is realized by an ideal clock distribution circuit, when two or more cell libraries can be used, a technology mapping method which assigns cells of gates of the given logic circuit by using integer linear programming is proposed. In experiments, we show the effectiveness of the proposed technology mapping method. | |
| Keyword | (in Japanese) | (See Japanese page) |
| (in English) | General-Synchronous Framework / Technology Mapping / Integer Linear Programming / / / / / | |
| Reference Info. | IEICE Tech. Rep., vol. 114, no. 328, VLD2014-83, pp. 87-92, Nov. 2014. | |
| Paper # | VLD2014-83 | |
| Date of Issue | 2014-11-19 (VLD, DC) | |
| ISSN | Print edition: ISSN 0913-5685 Online edition: ISSN 2432-6380 | |
| Copyright and reproduction |
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034) | |
| Download PDF | VLD2014-83 DC2014-37 |
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| Conference Information | |
| Committee | VLD DC IPSJ-SLDM CPSY RECONF ICD CPM |
| Conference Date | 2014-11-26 - 2014-11-28 |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | B-ConPlaza |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | Design Gaia 2014 -New Field of VLSI Design- |
| Paper Information | |
| Registration To | VLD |
| Conference Code | 2014-11-VLD-DC-SLDM-CPSY-RECONF-ICD-CPM |
| Language | Japanese |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | Technology Mapping Method for Low Power Consumption and High Performance in General-Synchronous Framework |
| Sub Title (in English) | |
| Keyword(1) | General-Synchronous Framework |
| Keyword(2) | Technology Mapping |
| Keyword(3) | Integer Linear Programming |
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| 1st Author's Name | Junki Kawaguchi |
| 1st Author's Affiliation | The University of Aizu (Univ. of Aizu) |
| 2nd Author's Name | Yukihide Kohira |
| 2nd Author's Affiliation | The University of Aizu (Univ. of Aizu) |
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| Speaker | Author-1 |
| Date Time | 2014-11-26 11:10:00 |
| Presentation Time | 25 minutes |
| Registration for | VLD |
| Paper # | VLD2014-83, DC2014-37 |
| Volume (vol) | vol.114 |
| Number (no) | no.328(VLD), no.329(DC) |
| Page | pp.87-92 |
| #Pages | 6 |
| Date of Issue | 2014-11-19 (VLD, DC) |
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