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| Presentation | 2014-11-26 09:40 Implementation of Multi-dimensional FPGA array HPC system-Vocalise for Numerical simulation and its Performance Evaluation Jiang Li, Hiromasa Kubo, Satoru Yokota, Yuichi Ogishima, Masatoshi Sekine (TUAT)  RECONF2014-35 |
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| Abstract | (in Japanese) | (See Japanese page) |
| (in English) | In recent years, the HPC systems with FPGAs increase. We have proposed the HPC system Vocalise with FPGA array. The FPGA array of Vocalise is consists of small FPGA cards which can achieve three-dimensional communications. The FPGA array is used scalable design, the system can implement the large-scale computing network to match the different object problem. As an example design, three-dimensional Poisson Equation is operated by a three-dimensional FPGA array. In the paper, the implementation of arithmetic circuits on 3D FPGA array, performance, power consumption and communication evaluation method among FPGAs were reported. |
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| Keyword | (in Japanese) | (See Japanese page) |
| (in English) | Vocalise / Multi-demensional FPGA array / Distributed computing / hw/sw complex / Configurable HPC / / / | |
| Reference Info. | IEICE Tech. Rep., vol. 114, no. 331, RECONF2014-35, pp. 7-12, Nov. 2014. | |
| Paper # | RECONF2014-35 | |
| Date of Issue | 2014-11-19 (RECONF) | |
| ISSN | Print edition: ISSN 0913-5685 Online edition: ISSN 2432-6380 | |
| Copyright and reproduction |
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034) | |
| Download PDF | RECONF2014-35 |
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| Conference Information | |
| Committee | VLD DC IPSJ-SLDM CPSY RECONF ICD CPM |
| Conference Date | 2014-11-26 - 2014-11-28 |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | B-ConPlaza |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | Design Gaia 2014 -New Field of VLSI Design- |
| Paper Information | |
| Registration To | RECONF |
| Conference Code | 2014-11-VLD-DC-SLDM-CPSY-RECONF-ICD-CPM |
| Language | Japanese |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | Implementation of Multi-dimensional FPGA array HPC system-Vocalise for Numerical simulation and its Performance Evaluation |
| Sub Title (in English) | |
| Keyword(1) | Vocalise |
| Keyword(2) | Multi-demensional FPGA array |
| Keyword(3) | Distributed computing |
| Keyword(4) | hw/sw complex |
| Keyword(5) | Configurable HPC |
| Keyword(6) | |
| Keyword(7) | |
| Keyword(8) | |
| 1st Author's Name | Jiang Li |
| 1st Author's Affiliation | Tokyo University of Agriculture and Technology (TUAT) |
| 2nd Author's Name | Hiromasa Kubo |
| 2nd Author's Affiliation | Tokyo University of Agriculture and Technology (TUAT) |
| 3rd Author's Name | Satoru Yokota |
| 3rd Author's Affiliation | Tokyo University of Agriculture and Technology (TUAT) |
| 4th Author's Name | Yuichi Ogishima |
| 4th Author's Affiliation | Tokyo University of Agriculture and Technology (TUAT) |
| 5th Author's Name | Masatoshi Sekine |
| 5th Author's Affiliation | Tokyo University of Agriculture and Technology (TUAT) |
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| Speaker | Author-1 |
| Date Time | 2014-11-26 09:40:00 |
| Presentation Time | 25 minutes |
| Registration for | RECONF |
| Paper # | RECONF2014-35 |
| Volume (vol) | vol.114 |
| Number (no) | no.331 |
| Page | pp.7-12 |
| #Pages | 6 |
| Date of Issue | 2014-11-19 (RECONF) |
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