Paper Abstract and Keywords |
Presentation |
2014-11-28 14:45
A Study of Power Optimization for Asynchronous Circuits with Bundled-data Implementation using Mobility of Operations Shunya Hosaka, Hiroshi Saito (Univ. Aizu) VLD2014-104 DC2014-58 |
Abstract |
(in Japanese) |
(See Japanese page) |
(in English) |
In this paper, we study a dynamic power optimization method for asynchronous circuits with bundled-data implementation using the mobility of operations. In asynchronous circuits, we can change the execution time of each operation freely under a given latency constraint. Therefore, the proposed method relaxes the execution time of operations which consume more power while it tightens the execution time of operations which consume less power. In the experiments, we evaluate the effect of the proposed method by comparing area, execution time, power consumption, and energy consumption among synchronous circuits and asynchronous circuits derived from synchronous register transfer level (RTL) models with and without the proposed method. |
Keyword |
(in Japanese) |
(See Japanese page) |
(in English) |
asynchronous circuits / mobility of operations / dynamic power optimization / RTL design / / / / |
Reference Info. |
IEICE Tech. Rep., vol. 114, no. 328, VLD2014-104, pp. 215-220, Nov. 2014. |
Paper # |
VLD2014-104 |
Date of Issue |
2014-11-19 (VLD, DC) |
ISSN |
Print edition: ISSN 0913-5685 Online edition: ISSN 2432-6380 |
Copyright and reproduction |
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034) |
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VLD2014-104 DC2014-58 |
Conference Information |
Committee |
VLD DC IPSJ-SLDM CPSY RECONF ICD CPM |
Conference Date |
2014-11-26 - 2014-11-28 |
Place (in Japanese) |
(See Japanese page) |
Place (in English) |
B-ConPlaza |
Topics (in Japanese) |
(See Japanese page) |
Topics (in English) |
Design Gaia 2014 -New Field of VLSI Design- |
Paper Information |
Registration To |
VLD |
Conference Code |
2014-11-VLD-DC-SLDM-CPSY-RECONF-ICD-CPM |
Language |
Japanese |
Title (in Japanese) |
(See Japanese page) |
Sub Title (in Japanese) |
(See Japanese page) |
Title (in English) |
A Study of Power Optimization for Asynchronous Circuits with Bundled-data Implementation using Mobility of Operations |
Sub Title (in English) |
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asynchronous circuits |
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mobility of operations |
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dynamic power optimization |
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RTL design |
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1st Author's Name |
Shunya Hosaka |
1st Author's Affiliation |
University of Aizu (Univ. Aizu) |
2nd Author's Name |
Hiroshi Saito |
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University of Aizu (Univ. Aizu) |
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Speaker |
Author-1 |
Date Time |
2014-11-28 14:45:00 |
Presentation Time |
25 minutes |
Registration for |
VLD |
Paper # |
VLD2014-104, DC2014-58 |
Volume (vol) |
vol.114 |
Number (no) |
no.328(VLD), no.329(DC) |
Page |
pp.215-220 |
#Pages |
6 |
Date of Issue |
2014-11-19 (VLD, DC) |
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