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Paper Abstract and Keywords
Presentation 2015-03-02 10:10
Proposal and evaluation of energy-efficient Network-on-Chip architecture with integrated packet and path switches
Takahide Ikeda, Yuichi Ohsita, Masayuki Murata (Osaka University) IN2014-128
Abstract (in Japanese) (See Japanese page) 
(in English) (Not available yet)
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Reference Info. IEICE Tech. Rep., vol. 114, no. 478, IN2014-128, pp. 43-48, March 2015.
Paper # IN2014-128 
Date of Issue 2015-02-23 (IN) 
ISSN Print edition: ISSN 0913-5685    Online edition: ISSN 2432-6380
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All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034)
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Conference Information
Committee NS IN  
Conference Date 2015-03-02 - 2015-03-03 
Place (in Japanese) (See Japanese page) 
Place (in English) Okinawa Convention Center 
Topics (in Japanese) (See Japanese page) 
Topics (in English) General 
Paper Information
Registration To IN 
Conference Code 2015-03-NS-IN 
Language Japanese 
Title (in Japanese) (See Japanese page) 
Sub Title (in Japanese) (See Japanese page) 
Title (in English) Proposal and evaluation of energy-efficient Network-on-Chip architecture with integrated packet and path switches 
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1st Author's Name Takahide Ikeda  
1st Author's Affiliation Osaka University (Osaka University)
2nd Author's Name Yuichi Ohsita  
2nd Author's Affiliation Osaka University (Osaka University)
3rd Author's Name Masayuki Murata  
3rd Author's Affiliation Osaka University (Osaka University)
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Date Time 2015-03-02 10:10:00 
Presentation Time 20 minutes 
Registration for IN 
Paper # IN2014-128 
Volume (vol) vol.114 
Number (no) no.478 
Page pp.43-48 
#Pages
Date of Issue 2015-02-23 (IN) 


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