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| Presentation | 2015-03-03 15:00 [Memorial Lecture] A Performance Enhanced Dual-switch Network-on-Chip Architecture Lian Zeng, Takahiro Watanabe (Waseda Univ.)  VLD2014-170 |
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| Abstract | (in Japanese) | (See Japanese page) |
| (in English) | Network-on-Chip (NoC) is an attractive solution for future systems on chip (SoC). The network performance depends critically on the performance of packets routing. However, as the network becomes more congested, packets will be blocked more frequently. It would result in degrading the network performance. In this article, we propose an innovative dual-switch allocation (DSA) design. By introducing two switch allocations, we can make utmost use of idle output ports. Experimental results show that our design significantly achieves the performance improvement in terms of throughput and latency at the cost of very little power overhead. | |
| Keyword | (in Japanese) | (See Japanese page) |
| (in English) | network-on-chip / dual-switch / performance enhanced / / / / / | |
| Reference Info. | IEICE Tech. Rep., vol. 114, no. 476, VLD2014-170, pp. 97-102, March 2015. | |
| Paper # | VLD2014-170 | |
| Date of Issue | 2015-02-23 (VLD) | |
| ISSN | Print edition: ISSN 0913-5685 Online edition: ISSN 2432-6380 | |
| Copyright and reproduction |
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034) | |
| Download PDF | VLD2014-170 |
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| Conference Information | |
| Committee | VLD |
| Conference Date | 2015-03-02 - 2015-03-04 |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | Okinawa Seinen Kaikan |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | |
| Paper Information | |
| Registration To | VLD |
| Conference Code | 2015-03-VLD |
| Language | English |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | A Performance Enhanced Dual-switch Network-on-Chip Architecture |
| Sub Title (in English) | |
| Keyword(1) | network-on-chip |
| Keyword(2) | dual-switch |
| Keyword(3) | performance enhanced |
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| 1st Author's Name | Lian Zeng |
| 1st Author's Affiliation | Waseda University (Waseda Univ.) |
| 2nd Author's Name | Takahiro Watanabe |
| 2nd Author's Affiliation | Waseda University (Waseda Univ.) |
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| Speaker | Author-1 |
| Date Time | 2015-03-03 15:00:00 |
| Presentation Time | 25 minutes |
| Registration for | VLD |
| Paper # | VLD2014-170 |
| Volume (vol) | vol.114 |
| Number (no) | no.476 |
| Page | pp.97-102 |
| #Pages | 6 |
| Date of Issue | 2015-02-23 (VLD) |
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