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Paper Abstract and Keywords
Presentation 2015-04-17 10:50
Design and Implementation of FPGA-based Sorting Accelerator
Ryohei Kobayashi, Kenji Kise (Tokyo Tech) CPSY2015-5 DC2015-5
Abstract (in Japanese) (See Japanese page) 
(in English) Sorting is an extremely important computation kernel that has been tried to be accelerated in a lot of fields, such as database, image processing, data compression and so on. We propose an FPGA-based accelerator that executes sorting at high speed. FPGA-based accelerators can achieve higher computation performance than CPUs and GPUs, because designers can implement circuits that realize application-specific pipelined hardware and data supply system. Our proposed FPGA accelerator uses two approaches: “Sorting Network” and “Merge Sorter Tree”. In this paper, we detail design and implementation of the proposed sorting accelerator, and evaluate this performance. As a result, the sorting speed of the proposed hardware is up to 10.06x than Intel Core i7-4770 operating at 3.4GHz.
Keyword (in Japanese) (See Japanese page) 
(in English) FPGA / Accelerator / Sorting / / / / /  
Reference Info. IEICE Tech. Rep., vol. 115, no. 7, CPSY2015-5, pp. 25-30, April 2015.
Paper # CPSY2015-5 
Date of Issue 2015-04-10 (CPSY, DC) 
ISSN Print edition: ISSN 0913-5685    Online edition: ISSN 2432-6380
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reproduction
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034)
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Conference Information
Committee DC CPSY  
Conference Date 2015-04-17 - 2015-04-17 
Place (in Japanese) (See Japanese page) 
Place (in English)  
Topics (in Japanese) (See Japanese page) 
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Paper Information
Registration To CPSY 
Conference Code 2015-04-DC-CPSY 
Language Japanese 
Title (in Japanese) (See Japanese page) 
Sub Title (in Japanese) (See Japanese page) 
Title (in English) Design and Implementation of FPGA-based Sorting Accelerator 
Sub Title (in English)  
Keyword(1) FPGA  
Keyword(2) Accelerator  
Keyword(3) Sorting  
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1st Author's Name Ryohei Kobayashi  
1st Author's Affiliation Tokyo Institute of Technology (Tokyo Tech)
2nd Author's Name Kenji Kise  
2nd Author's Affiliation Tokyo Institute of Technology (Tokyo Tech)
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Speaker Author-1 
Date Time 2015-04-17 10:50:00 
Presentation Time 25 minutes 
Registration for CPSY 
Paper # CPSY2015-5, DC2015-5 
Volume (vol) vol.115 
Number (no) no.7(CPSY), no.8(DC) 
Page pp.25-30 
#Pages
Date of Issue 2015-04-10 (CPSY, DC) 


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