Paper Abstract and Keywords |
Presentation |
2015-06-16 15:35
A Study on Function Test of Latch-based Asynchronous Pipeline Circuits Daiki Toyoshima, Kyohei Terayama, Atsushi Kurokawa, Masashi Imai (Hirosaki Univ.) DC2015-19 |
Abstract |
(in Japanese) |
(See Japanese page) |
(in English) |
Asynchronous MOUSETRAP pipeline circuit is a simple and fast circuit thanks to the 2-phase handshaking protocol which has no return-to-zero overhead. In the MOUSETRAP circuits, D-latch cells are used as storage elements instead of D-flip flop cells. We have presented two scan D-latches in order to achieve a full scan test of the MOUSETRAP circuit, and have evaluated them using standard cell library. In this paper, a transistor level circuit implementation of the scan D-latch is proposed. Then, evaluation results using the ISCAS89 benchmark combinational circuits are shown. |
Keyword |
(in Japanese) |
(See Japanese page) |
(in English) |
Asynchronous circuits / full scan test / MOUSETRAP pipeline circuits / scan D-latch / / / / |
Reference Info. |
IEICE Tech. Rep., vol. 115, no. 86, DC2015-19, pp. 19-24, June 2015. |
Paper # |
DC2015-19 |
Date of Issue |
2015-06-09 (DC) |
ISSN |
Print edition: ISSN 0913-5685 Online edition: ISSN 2432-6380 |
Copyright and reproduction |
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034) |
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DC2015-19 |
Conference Information |
Committee |
DC |
Conference Date |
2015-06-16 - 2015-06-16 |
Place (in Japanese) |
(See Japanese page) |
Place (in English) |
Kikai-Shinko-Kaikan Bldg. |
Topics (in Japanese) |
(See Japanese page) |
Topics (in English) |
Reliable design and Test, etc. |
Paper Information |
Registration To |
DC |
Conference Code |
2015-06-DC |
Language |
Japanese |
Title (in Japanese) |
(See Japanese page) |
Sub Title (in Japanese) |
(See Japanese page) |
Title (in English) |
A Study on Function Test of Latch-based Asynchronous Pipeline Circuits |
Sub Title (in English) |
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Keyword(1) |
Asynchronous circuits |
Keyword(2) |
full scan test |
Keyword(3) |
MOUSETRAP pipeline circuits |
Keyword(4) |
scan D-latch |
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1st Author's Name |
Daiki Toyoshima |
1st Author's Affiliation |
Hirosaki University (Hirosaki Univ.) |
2nd Author's Name |
Kyohei Terayama |
2nd Author's Affiliation |
Hirosaki University (Hirosaki Univ.) |
3rd Author's Name |
Atsushi Kurokawa |
3rd Author's Affiliation |
Hirosaki University (Hirosaki Univ.) |
4th Author's Name |
Masashi Imai |
4th Author's Affiliation |
Hirosaki University (Hirosaki Univ.) |
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Speaker |
Author-4 |
Date Time |
2015-06-16 15:35:00 |
Presentation Time |
25 minutes |
Registration for |
DC |
Paper # |
DC2015-19 |
Volume (vol) |
vol.115 |
Number (no) |
no.86 |
Page |
pp.19-24 |
#Pages |
6 |
Date of Issue |
2015-06-09 (DC) |
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