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Paper Abstract and Keywords
Presentation 2015-06-17 11:10
Accelerating techniques for test pattern compaction for large circuits
Yusuke Matsunaga (Kyushu Univ.) CAS2015-5 VLD2015-12 SIP2015-36 MSS2015-5
Abstract (in Japanese) (See Japanese page) 
(in English) This paper presents accelerating techniques for test pattern compaction algorithm applicable for
large scale circuits.
New concepts called `sufficient assignments' and `mandatory
assignments' for fault detection are proposed.
Novel algorithms checking fault dominance and fault compatibility
utilizing these concepts are also described.
The experimental results show that the proposed techniques achieve
big speed up while maintainig the test compaction capability similar.
Keyword (in Japanese) (See Japanese page) 
(in English) test pattern generation / test pattern compaction / SAT / / / / /  
Reference Info. IEICE Tech. Rep., vol. 115, no. 88, VLD2015-12, pp. 25-30, June 2015.
Paper # VLD2015-12 
Date of Issue 2015-06-10 (CAS, VLD, SIP, MSS) 
ISSN Print edition: ISSN 0913-5685    Online edition: ISSN 2432-6380
Copyright
and
reproduction
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034)
Download PDF CAS2015-5 VLD2015-12 SIP2015-36 MSS2015-5

Conference Information
Committee MSS CAS SIP VLD  
Conference Date 2015-06-17 - 2015-06-18 
Place (in Japanese) (See Japanese page) 
Place (in English) Otaru University of Commerce 
Topics (in Japanese) (See Japanese page) 
Topics (in English) System, signal processing and related topics 
Paper Information
Registration To VLD 
Conference Code 2015-06-MSS-CAS-SIP-VLD 
Language Japanese 
Title (in Japanese) (See Japanese page) 
Sub Title (in Japanese) (See Japanese page) 
Title (in English) Accelerating techniques for test pattern compaction for large circuits 
Sub Title (in English)  
Keyword(1) test pattern generation  
Keyword(2) test pattern compaction  
Keyword(3) SAT  
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1st Author's Name Yusuke Matsunaga  
1st Author's Affiliation Kyushu University (Kyushu Univ.)
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Speaker Author-1 
Date Time 2015-06-17 11:10:00 
Presentation Time 25 minutes 
Registration for VLD 
Paper # CAS2015-5, VLD2015-12, SIP2015-36, MSS2015-5 
Volume (vol) vol.115 
Number (no) no.87(CAS), no.88(VLD), no.89(SIP), no.90(MSS) 
Page pp.25-30 
#Pages
Date of Issue 2015-06-10 (CAS, VLD, SIP, MSS) 


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