2016-02-29 17:00
An ASIC Implementation of Hardware Logarithm Generator for Digital Signal Processing in Communication Systems ○Van-Thuan Sai・Van-Phuc Hoang（LQDTU）
抄録
（和）
In this paper, we present an efficient hardware approximation for the binary logarithm function which is highly required for digital signal processing in communication systems . The proposed logarithm generator employs multiple linear segments approach combined with a look-up table (LUT) and a parameter optimization algorithm to achieve the good trade-off between computation speed and resource efficiency. The implementation results in both FPGA and 65nm CMOS ASIC technology are also presented and discussed.
（英）
In this paper, we present an efficient hardware approximation for the binary logarithm function which is highly required for digital signal processing in communication systems . The proposed logarithm generator employs multiple linear segments approach combined with a look-up table (LUT) and a parameter optimization algorithm to achieve the good trade-off between computation speed and resource efficiency. The implementation results in both FPGA and 65nm CMOS ASIC technology are also presented and discussed.