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Paper Abstract and Keywords
Presentation 2016-02-29 17:00
An ASIC Implementation of Hardware Logarithm Generator for Digital Signal Processing in Communication Systems
Van-Thuan Sai, Van-Phuc Hoang (LQDTU)
Abstract (in Japanese) (See Japanese page) 
(in English) In this paper, we present an efficient hardware approximation for the binary logarithm function which is highly required for digital signal processing in communication systems . The proposed logarithm generator employs multiple linear segments approach combined with a look-up table (LUT) and a parameter optimization algorithm to achieve the good trade-off between computation speed and resource efficiency. The implementation results in both FPGA and 65nm CMOS ASIC technology are also presented and discussed.
Keyword (in Japanese) (See Japanese page) 
(in English) logarithm hardware approximation / 65nm CMOS / SOTB / low power / / / /  
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Conference Information
Committee AP  
Conference Date 2016-02-29 - 2016-03-01 
Place (in Japanese) (See Japanese page) 
Place (in English) Telecommunications University, Nha Trang, Vietnam 
Topics (in Japanese) (See Japanese page) 
Topics (in English) The 2016 Vietnam-Japan International Symposium on Antennas and Propagation 
Paper Information
Registration To AP 
Conference Code 2016-02-AP 
Language English 
Title (in Japanese) (See Japanese page) 
Sub Title (in Japanese) (See Japanese page) 
Title (in English) An ASIC Implementation of Hardware Logarithm Generator for Digital Signal Processing in Communication Systems 
Sub Title (in English)  
Keyword(1) logarithm hardware approximation  
Keyword(2) 65nm CMOS  
Keyword(3) SOTB  
Keyword(4) low power  
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1st Author's Name Van-Thuan Sai  
1st Author's Affiliation Le Quy Don Technical University (LQDTU)
2nd Author's Name Van-Phuc Hoang  
2nd Author's Affiliation Le Quy Don Technical University (LQDTU)
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Speaker Author-1 
Date Time 2016-02-29 17:00:00 
Presentation Time 15 minutes 
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