Paper Abstract and Keywords |
Presentation |
2016-03-01 14:45
IP Design using High-Level Synthesis Design Flow Masato Tatsuoka, Ken Imanishi, Hidenori Nakaishi, Takeshi Toyoyama (SNI) VLD2015-126 |
Abstract |
(in Japanese) |
(See Japanese page) |
(in English) |
In this paper we will describe practical experiences about the use of high level synthesis technologies to achieve higher performance, higher quality, and lower power for IP designs as compared to traditional RTL design. We could achieve a time-to-market requirement and a better PPA compared to the hand RTL design IP. We will show how the introduction of three key techniques: interface-based design, architectural exploration and congestion-aware high level synthesis were utilized to achieve higher quality IP designs. |
Keyword |
(in Japanese) |
(See Japanese page) |
(in English) |
High Level Synthesis / Routing Congestion / architectural exploration / interface-based design / verification / / / |
Reference Info. |
IEICE Tech. Rep., vol. 115, no. 465, VLD2015-126, pp. 87-92, Feb. 2016. |
Paper # |
VLD2015-126 |
Date of Issue |
2016-02-22 (VLD) |
ISSN |
Print edition: ISSN 0913-5685 Online edition: ISSN 2432-6380 |
Copyright and reproduction |
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034) |
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VLD2015-126 |
Conference Information |
Committee |
VLD |
Conference Date |
2016-02-29 - 2016-03-02 |
Place (in Japanese) |
(See Japanese page) |
Place (in English) |
Okinawa Seinen Kaikan |
Topics (in Japanese) |
(See Japanese page) |
Topics (in English) |
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Paper Information |
Registration To |
VLD |
Conference Code |
2016-02-VLD |
Language |
Japanese |
Title (in Japanese) |
(See Japanese page) |
Sub Title (in Japanese) |
(See Japanese page) |
Title (in English) |
IP Design using High-Level Synthesis Design Flow |
Sub Title (in English) |
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Keyword(1) |
High Level Synthesis |
Keyword(2) |
Routing Congestion |
Keyword(3) |
architectural exploration |
Keyword(4) |
interface-based design |
Keyword(5) |
verification |
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1st Author's Name |
Masato Tatsuoka |
1st Author's Affiliation |
Socionext Inc. (SNI) |
2nd Author's Name |
Ken Imanishi |
2nd Author's Affiliation |
Socionext Inc. (SNI) |
3rd Author's Name |
Hidenori Nakaishi |
3rd Author's Affiliation |
Socionext Inc. (SNI) |
4th Author's Name |
Takeshi Toyoyama |
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Socionext Inc. (SNI) |
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Speaker |
Author-1 |
Date Time |
2016-03-01 14:45:00 |
Presentation Time |
25 minutes |
Registration for |
VLD |
Paper # |
VLD2015-126 |
Volume (vol) |
vol.115 |
Number (no) |
no.465 |
Page |
pp.87-92 |
#Pages |
6 |
Date of Issue |
2016-02-22 (VLD) |
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