Paper Abstract and Keywords |
Presentation |
2016-05-11 14:30
A High-Level Synthesis Algorithm using Critical Path Optimization Based Operation Chainings for RDR Architectures Kotaro Terada, Masao Yanagisawa, Nozomu Togawa (Waseda Univ.) VLD2016-4 |
Abstract |
(in Japanese) |
(See Japanese page) |
(in English) |
In deep-submicron era, interconnection delays are not negligible even in high-level synthesis. RDR (Regular Distributed Register) architecture has been proposed to cope with this problem. Operation chaining, which pack adjacent operations into smaller control steps, is an effective technique to reduce the overall latency. In this paper, we propose a high-level synthesis algorithm targeting RDR architecture using critical path optimization based operation chainings to synthesize high-performance circuits. Experimental results show that our algorithm reduces the latency compared to the conventional algorithm with operation chainings for RDR architecture. |
Keyword |
(in Japanese) |
(See Japanese page) |
(in English) |
high-level synthesis (HLS) / distributed-register architecture / floorplan / interconnection delay / operation chaining / / / |
Reference Info. |
IEICE Tech. Rep., vol. 116, no. 21, VLD2016-4, pp. 41-46, May 2016. |
Paper # |
VLD2016-4 |
Date of Issue |
2016-05-04 (VLD) |
ISSN |
Print edition: ISSN 0913-5685 Online edition: ISSN 2432-6380 |
Copyright and reproduction |
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034) |
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VLD2016-4 |
Conference Information |
Committee |
VLD IPSJ-SLDM |
Conference Date |
2016-05-11 - 2016-05-11 |
Place (in Japanese) |
(See Japanese page) |
Place (in English) |
Kitakyushu International Conference Center |
Topics (in Japanese) |
(See Japanese page) |
Topics (in English) |
System Design, etc. |
Paper Information |
Registration To |
VLD |
Conference Code |
2016-05-VLD-SLDM |
Language |
Japanese |
Title (in Japanese) |
(See Japanese page) |
Sub Title (in Japanese) |
(See Japanese page) |
Title (in English) |
A High-Level Synthesis Algorithm using Critical Path Optimization Based Operation Chainings for RDR Architectures |
Sub Title (in English) |
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Keyword(1) |
high-level synthesis (HLS) |
Keyword(2) |
distributed-register architecture |
Keyword(3) |
floorplan |
Keyword(4) |
interconnection delay |
Keyword(5) |
operation chaining |
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1st Author's Name |
Kotaro Terada |
1st Author's Affiliation |
Waseda University (Waseda Univ.) |
2nd Author's Name |
Masao Yanagisawa |
2nd Author's Affiliation |
Waseda University (Waseda Univ.) |
3rd Author's Name |
Nozomu Togawa |
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Waseda University (Waseda Univ.) |
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Speaker |
Author-1 |
Date Time |
2016-05-11 14:30:00 |
Presentation Time |
25 minutes |
Registration for |
VLD |
Paper # |
VLD2016-4 |
Volume (vol) |
vol.116 |
Number (no) |
no.21 |
Page |
pp.41-46 |
#Pages |
6 |
Date of Issue |
2016-05-04 (VLD) |
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