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Paper Abstract and Keywords
Presentation 2016-05-17 14:00
[Poster Presentation] Advanced FPGA/ASIC Development
Teemu Aura, Olga Kayo (Nokia), Jukka Lahti, Janne Janhunen (Univ. of Oulu)
Abstract (in Japanese) (See Japanese page) 
(in English) Novel 5G innovations and technologies are rapidly coming into market. One of the main requirement for the new systems is to have a short time to market development process. In this paper, we present advanced FPGA development with Vivado high level synthesis (HLS) tool by Xilinx. We demonstrate how the usage of the tool speeds up the FPGA development process and reduce time to market. We go through the example of matrix-matrix multiplication algorithm to show possible optimization of the implementation that results in optimizing FPGA resource usage (flip-flops, DSP cores, look-up tables).
Keyword (in Japanese) (See Japanese page) 
(in English) FPGA/ASIC Design / FPGA/ASIC Development / Vivado / FPGA/ASIC Resource Optimization / / / /  
Reference Info. IEICE Tech. Rep.
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Conference Information
Committee SR RCC MICT RCS SRW  
Conference Date 2016-05-16 - 2016-05-17 
Place (in Japanese) (See Japanese page) 
Place (in English) Hotel Lasaretti, Oulu, Finland 
Topics (in Japanese) (See Japanese page) 
Topics (in English) SmartCom 2016 
Paper Information
Registration To SR 
Conference Code 2016-05-SR-RCC-MICT-RCS-SRW 
Language English 
Title (in Japanese) (See Japanese page) 
Sub Title (in Japanese) (See Japanese page) 
Title (in English) Advanced FPGA/ASIC Development 
Sub Title (in English)  
Keyword(1) FPGA/ASIC Design  
Keyword(2) FPGA/ASIC Development  
Keyword(3) Vivado  
Keyword(4) FPGA/ASIC Resource Optimization  
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1st Author's Name Teemu Aura  
1st Author's Affiliation Nokia (Nokia)
2nd Author's Name Olga Kayo  
2nd Author's Affiliation Nokia (Nokia)
3rd Author's Name Jukka Lahti  
3rd Author's Affiliation University of Oulu (Univ. of Oulu)
4th Author's Name Janne Janhunen  
4th Author's Affiliation University of Oulu (Univ. of Oulu)
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Speaker Author-1 
Date Time 2016-05-17 14:00:00 
Presentation Time 100 minutes 
Registration for SR 
Paper #  
Volume (vol) vol.116 
Number (no) no.29(SR), no.30(SRW) 
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