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Paper Abstract and Keywords
Presentation 2016-11-28 14:40
Evaluation of Soft Error Hardness of FinFET and FDSOI Processes by the PHITS-TCAD Simulation System
Shigehiro Umehara, Jun Furuta, Kazutoshi Kobayashi (KIT) VLD2016-50 DC2016-44
Abstract (in Japanese) (See Japanese page) 
(in English) The impact of soft errors has been serious with process scaling of integrated circuits. Simulation methods for soft errors in FDSOI and FinFET are indispensable. We alalyze the soft error tolerance in 28-nm FDSOI and 22-nm FinFET processes by the PHIT-TCAD simulation system. It consists of two parts, a particle transport simulation by PHITS (Particle and Heavy Ion Transport code System) and device simulations. We investigate the soft error rates on 28-nm FDSOI and 22-nm FinFET by the PHITS-TCAD simulation. The soft error tolerance in 22-nm FinFET is 10 times or more stronger than that in 28-nm FDSOI in supply voltages from 1V to 0.4V.
Keyword (in Japanese) (See Japanese page) 
(in English) Soft Error / FDSOI / FinFET / TCAD / PHITS / / /  
Reference Info. IEICE Tech. Rep., vol. 116, no. 330, VLD2016-50, pp. 37-41, Nov. 2016.
Paper # VLD2016-50 
Date of Issue 2016-11-21 (VLD, DC) 
ISSN Print edition: ISSN 0913-5685    Online edition: ISSN 2432-6380
Copyright
and
reproduction		 All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034)
Download PDF VLD2016-50 DC2016-44

Conference Information
Committee VLD DC CPSY RECONF CPM ICD IE  
Conference Date 2016-11-28 - 2016-11-30 
Place (in Japanese) (See Japanese page) 
Place (in English) Ritsumeikan University, Osaka Ibaraki Campus 
Topics (in Japanese) (See Japanese page) 
Topics (in English) Design Gaia 2016 -New Field of VLSI Design- 
Paper Information
Registration To VLD 
Conference Code 2016-11-VLD-DC-CPSY-RECONF-CPM-ICD-IE 
Language Japanese 
Title (in Japanese) (See Japanese page) 
Sub Title (in Japanese) (See Japanese page) 
Title (in English) Evaluation of Soft Error Hardness of FinFET and FDSOI Processes by the PHITS-TCAD Simulation System 
Sub Title (in English)  
Keyword(1) Soft Error  
Keyword(2) FDSOI  
Keyword(3) FinFET  
Keyword(4) TCAD  
Keyword(5) PHITS  
Keyword(6)  
Keyword(7)  
Keyword(8)  
1st Author's Name Shigehiro Umehara  
1st Author's Affiliation Kyoto Institute of Technology (KIT)
2nd Author's Name Jun Furuta  
2nd Author's Affiliation Kyoto Institute of Technology (KIT)
3rd Author's Name Kazutoshi Kobayashi  
3rd Author's Affiliation Kyoto Institute of Technology (KIT)
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Speaker Author-1 
Date Time 2016-11-28 14:40:00 
Presentation Time 25 minutes 
Registration for VLD 
Paper # VLD2016-50, DC2016-44 
Volume (vol) vol.116 
Number (no) no.330(VLD), no.331(DC) 
Page pp.37-41 
#Pages 5 
Date of Issue 2016-11-21 (VLD, DC) 

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