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| Presentation | 2017-01-24 13:30 Implementation of Path Profiler Using Loop Block for Dynamic Behavior Analysis of Nested Loops Yuki Kikuchi, Kanemitsu Ootsu, Takanobu Baba, Takashi Yokota, Takeshi Ohkawa (Utsunomiya Univ.)  VLD2016-85 CPSY2016-121 RECONF2016-66 |
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| Abstract | (in Japanese) | (See Japanese page) |
| (in English) | Recently, heterogeneous multi-core processer is spreading. We should exactly understand both static and dynamic behavior of target programs for realizing effective parallel processing according to core with various characteristics. In particular, the acquisition of dynamic information is indispensable to realize effective parallel processing. We have developed a path profiler which can acquire profile information to realizing effective parallel processing for a loop. However, when the former profiler analyzes nested loops, there is a problem that the analysis except the most inner loop had difficult. It is possible for path profiler by the analysis for each hierarchy for nested loops by introducing a loop block. In this paper, we show the implementation of our profiler, and the operation of the profiler. |
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| Keyword | (in Japanese) | (See Japanese page) |
| (in English) | dynamic behavior analysis / loop block / heterogeneous multi-core / / / / / | |
| Reference Info. | IEICE Tech. Rep., vol. 116, no. 416, CPSY2016-121, pp. 103-108, Jan. 2017. | |
| Paper # | CPSY2016-121 | |
| Date of Issue | 2017-01-16 (VLD, CPSY, RECONF) | |
| ISSN | Print edition: ISSN 0913-5685 Online edition: ISSN 2432-6380 | |
| Copyright and reproduction |
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034) | |
| Download PDF | VLD2016-85 CPSY2016-121 RECONF2016-66 |
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| Conference Information | |
| Committee | CPSY RECONF VLD IPSJ-SLDM IPSJ-ARC |
| Conference Date | 2017-01-23 - 2017-01-25 |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | Hiyoshi Campus, Keio Univ. |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | FPGA Applications, etc |
| Paper Information | |
| Registration To | CPSY |
| Conference Code | 2017-01-CPSY-RECONF-VLD-SLDM-ARC |
| Language | Japanese |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | Implementation of Path Profiler Using Loop Block for Dynamic Behavior Analysis of Nested Loops |
| Sub Title (in English) | |
| Keyword(1) | dynamic behavior analysis |
| Keyword(2) | loop block |
| Keyword(3) | heterogeneous multi-core |
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| 1st Author's Name | Yuki Kikuchi |
| 1st Author's Affiliation | Utsunomiya University (Utsunomiya Univ.) |
| 2nd Author's Name | Kanemitsu Ootsu |
| 2nd Author's Affiliation | Utsunomiya University (Utsunomiya Univ.) |
| 3rd Author's Name | Takanobu Baba |
| 3rd Author's Affiliation | Utsunomiya University (Utsunomiya Univ.) |
| 4th Author's Name | Takashi Yokota |
| 4th Author's Affiliation | Utsunomiya University (Utsunomiya Univ.) |
| 5th Author's Name | Takeshi Ohkawa |
| 5th Author's Affiliation | Utsunomiya University (Utsunomiya Univ.) |
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| Speaker | Author-1 |
| Date Time | 2017-01-24 13:30:00 |
| Presentation Time | 25 minutes |
| Registration for | CPSY |
| Paper # | VLD2016-85, CPSY2016-121, RECONF2016-66 |
| Volume (vol) | vol.116 |
| Number (no) | no.415(VLD), no.416(CPSY), no.417(RECONF) |
| Page | pp.103-108 |
| #Pages | 6 |
| Date of Issue | 2017-01-16 (VLD, CPSY, RECONF) |
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