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Paper Abstract and Keywords
Presentation 2017-03-03 13:00
An Approach to Logic Optimization Using Permissible Functions for Error-Tolerant Application
Shinya Iwasaki, Hideyuki Ichihara, Tsuyoshi Iwagaki, Tomoo Inoue (Hiroshima City Univ.) VLD2016-128
Abstract (in Japanese) (See Japanese page) 
(in English) Error-tolerant application, such as image processing, machine learning and so on, is application that can tolerate specific errors, whose frequency and/or severity are within certain limits. This error tolerability is greatly instrumental in simplifying logic circuits for such application. In this paper, we focus on logic simplification problem using permissible functions for error-tolerant application. To solve this problem efficiently, we represent permissible functions with BDDs (Binary Decision Diagrams) and propose heuristic algorithms for solving this problem by utilizing characteristics of the BDD representation. In experiment, we also present a scheme to solve this problem with ILP (Integer Linear Programming) solver and compare the obtained optimum solutions with our results. Experimental results show that the proposed algorithm can derive optimum or quasi-optimal solutions efficiently.
Keyword (in Japanese) (See Japanese page) 
(in English) transduction method / error rate / don't-care / equivalence checking / inclusion checking / / /  
Reference Info. IEICE Tech. Rep., vol. 116, no. 478, VLD2016-128, pp. 145-150, March 2017.
Paper # VLD2016-128 
Date of Issue 2017-02-22 (VLD) 
ISSN Print edition: ISSN 0913-5685    Online edition: ISSN 2432-6380
Copyright
and
reproduction		 All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034)
Download PDF VLD2016-128

Conference Information
Committee VLD  
Conference Date 2017-03-01 - 2017-03-03 
Place (in Japanese) (See Japanese page) 
Place (in English) Okinawa Seinen Kaikan 
Topics (in Japanese) (See Japanese page) 
Topics (in English)  
Paper Information
Registration To VLD 
Conference Code 2017-03-VLD 
Language Japanese 
Title (in Japanese) (See Japanese page) 
Sub Title (in Japanese) (See Japanese page) 
Title (in English) An Approach to Logic Optimization Using Permissible Functions for Error-Tolerant Application 
Sub Title (in English)  
Keyword(1) transduction method  
Keyword(2) error rate  
Keyword(3) don't-care  
Keyword(4) equivalence checking  
Keyword(5) inclusion checking  
Keyword(6)  
Keyword(7)  
Keyword(8)  
1st Author's Name Shinya Iwasaki  
1st Author's Affiliation Hiroshima City University (Hiroshima City Univ.)
2nd Author's Name Hideyuki Ichihara  
2nd Author's Affiliation Hiroshima City University (Hiroshima City Univ.)
3rd Author's Name Tsuyoshi Iwagaki  
3rd Author's Affiliation Hiroshima City University (Hiroshima City Univ.)
4th Author's Name Tomoo Inoue  
4th Author's Affiliation Hiroshima City University (Hiroshima City Univ.)
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Speaker Author-1 
Date Time 2017-03-03 13:00:00 
Presentation Time 25 minutes 
Registration for VLD 
Paper # VLD2016-128 
Volume (vol) vol.116 
Number (no) no.478 
Page pp.145-150 
#Pages 6 
Date of Issue 2017-02-22 (VLD) 

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