Paper Abstract and Keywords |
Presentation |
2017-11-06 14:55
Leakage Energy Reduction for Digital Embedded Memory using Dynamic Multi Body Bias Control Yusuke Yoshida, Kimiyoshi Usami (SIT) VLD2017-33 DC2017-39 |
Abstract |
(in Japanese) |
(See Japanese page) |
(in English) |
Embedded memory macros are major central building blocks of any microprocessor and greatly affect power dissipation. In this paper, we focus on the Standard Cell based Memory (SCM) as a digital memory instead of SRAM macros. We propose a dynamic multi body-bias control technique which keeps data retention margin comfortable and reduces leakage energy under the variations. Post layout simulation showed that the proposed approach allowed us to reduce leakage energy by 37% and 48% at the maximum as compared to the conventional body bias control and Multi-Vth designs, respectively. |
Keyword |
(in Japanese) |
(See Japanese page) |
(in English) |
Body Bias / Standard Cell based Memory / Low voltage operation / Low energy / Variation tolerance / / / |
Reference Info. |
IEICE Tech. Rep., vol. 117, no. 273, VLD2017-33, pp. 37-42, Nov. 2017. |
Paper # |
VLD2017-33 |
Date of Issue |
2017-10-30 (VLD, DC) |
ISSN |
Print edition: ISSN 0913-5685 Online edition: ISSN 2432-6380 |
Copyright and reproduction |
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034) |
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VLD2017-33 DC2017-39 |
Conference Information |
Committee |
VLD DC CPSY RECONF CPM ICD IE IPSJ-SLDM |
Conference Date |
2017-11-06 - 2017-11-08 |
Place (in Japanese) |
(See Japanese page) |
Place (in English) |
Kumamoto-Kenminkouryukan Parea |
Topics (in Japanese) |
(See Japanese page) |
Topics (in English) |
Design Gaia 2017 -New Field of VLSI Design- |
Paper Information |
Registration To |
VLD |
Conference Code |
2017-11-VLD-DC-CPSY-RECONF-CPM-ICD-IE-SLDM-EMB-ARC |
Language |
Japanese |
Title (in Japanese) |
(See Japanese page) |
Sub Title (in Japanese) |
(See Japanese page) |
Title (in English) |
Leakage Energy Reduction for Digital Embedded Memory using Dynamic Multi Body Bias Control |
Sub Title (in English) |
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Keyword(1) |
Body Bias |
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Standard Cell based Memory |
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Low voltage operation |
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Low energy |
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Variation tolerance |
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1st Author's Name |
Yusuke Yoshida |
1st Author's Affiliation |
Shibaura Institute of Technology (SIT) |
2nd Author's Name |
Kimiyoshi Usami |
2nd Author's Affiliation |
Shibaura Institute of Technology (SIT) |
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Speaker |
Author-1 |
Date Time |
2017-11-06 14:55:00 |
Presentation Time |
25 minutes |
Registration for |
VLD |
Paper # |
VLD2017-33, DC2017-39 |
Volume (vol) |
vol.117 |
Number (no) |
no.273(VLD), no.274(DC) |
Page |
pp.37-42 |
#Pages |
6 |
Date of Issue |
2017-10-30 (VLD, DC) |
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