Paper Abstract and Keywords |
Presentation |
2018-01-19 16:40
Mutant Generation of Performance Tests for LLVM Back-Ends Kenji Tanaka, Nagisa Ishiura (Kwansei Gakuin Univ.), Masanari Nishimura, Akiya Fukui (Renesas) VLD2017-88 CPSY2017-132 RECONF2017-76 |
Abstract |
(in Japanese) |
(See Japanese page) |
(in English) |
This article presents a method of testing optimization capability of LLVM back-ends by generating functionally equivalent test mutants from existing test programs. Since the LLVM back-ends perform various target dependent and peephole optimization as well as transformations for code generation, it is necessary to test if optimization is properly done as designed to enhance performance, not to mention if generated codes are correct. Test programs for the performance test are usually developed manually by compiler designers, which do not always provide enough variation to cover corner cases. The method in this article attempts to augment test cases by generating mutants from existing test programs. The mutation in our method is designed not to change the functionality of the original test programs, so that insufficient optimization is detected by mechanical comparison of assembly codes. In a preliminary experiment on the LLVM 6.0.0 back-end for x86_64, a tool based on the proposed method has found two interesting cases which might contribute toward performance improvement of the back-end. |
Keyword |
(in Japanese) |
(See Japanese page) |
(in English) |
LLVM IR / Back-Ends / Mutation / Optimization / / / / |
Reference Info. |
IEICE Tech. Rep., vol. 117, no. 377, VLD2017-88, pp. 169-174, Jan. 2018. |
Paper # |
VLD2017-88 |
Date of Issue |
2018-01-11 (VLD, CPSY, RECONF) |
ISSN |
Print edition: ISSN 0913-5685 Online edition: ISSN 2432-6380 |
Copyright and reproduction |
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034) |
Download PDF |
VLD2017-88 CPSY2017-132 RECONF2017-76 |
Conference Information |
Committee |
IPSJ-ARC VLD CPSY RECONF IPSJ-SLDM |
Conference Date |
2018-01-18 - 2018-01-19 |
Place (in Japanese) |
(See Japanese page) |
Place (in English) |
Raiosha, Hiyoshi Campus, Keio University |
Topics (in Japanese) |
(See Japanese page) |
Topics (in English) |
FPGA Applications, etc |
Paper Information |
Registration To |
VLD |
Conference Code |
2018-01-ARC-VLD-CPSY-RECONF-SLDM |
Language |
Japanese |
Title (in Japanese) |
(See Japanese page) |
Sub Title (in Japanese) |
(See Japanese page) |
Title (in English) |
Mutant Generation of Performance Tests for LLVM Back-Ends |
Sub Title (in English) |
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Keyword(1) |
LLVM IR |
Keyword(2) |
Back-Ends |
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Mutation |
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Optimization |
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1st Author's Name |
Kenji Tanaka |
1st Author's Affiliation |
Kwansei Gakuin University (Kwansei Gakuin Univ.) |
2nd Author's Name |
Nagisa Ishiura |
2nd Author's Affiliation |
Kwansei Gakuin University (Kwansei Gakuin Univ.) |
3rd Author's Name |
Masanari Nishimura |
3rd Author's Affiliation |
Renesas Electronics Corporation (Renesas) |
4th Author's Name |
Akiya Fukui |
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Renesas Electronics Corporation (Renesas) |
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Speaker |
Author-1 |
Date Time |
2018-01-19 16:40:00 |
Presentation Time |
25 minutes |
Registration for |
VLD |
Paper # |
VLD2017-88, CPSY2017-132, RECONF2017-76 |
Volume (vol) |
vol.117 |
Number (no) |
no.377(VLD), no.378(CPSY), no.379(RECONF) |
Page |
pp.169-174 |
#Pages |
6 |
Date of Issue |
2018-01-11 (VLD, CPSY, RECONF) |
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