Paper Abstract and Keywords |
Presentation |
2018-03-01 09:50
Clustering for Reduction of Power Consumption and Area on Post-Silicon Delay Tuning Kota Muroi, Yukihide Kohira (Univ. of Aizu) VLD2017-107 |
Abstract |
(in Japanese) |
(See Japanese page) |
(in English) |
Due to progressing process technology, yield of chips is reduced by timing violation caused by delay variation of gates and wires in fabrication. Recently, post-silicon delay tuning, which inserts programmable delay elements (PDEs) into clock tree before the fabrication and sets the delays of the PDEs to recover the timing violation after the fabrication, is promising to improve the yield. In an existing method, since the PDE is constructed by a buffer chain and a demultiplexer and it is inserted for each register, power consumption and circuit area are increased drastically in comparison with conventional clock synchronous circuits. In this paper, a PDE structure is proposed to reduce the circuit area. Moreover, a clustering method, in which some PDEs are merged into a PDE and a PDE is inserted for multiple registers, is proposed to reduce the power consumption and the circuit area. |
Keyword |
(in Japanese) |
(See Japanese page) |
(in English) |
Post-silicon delay tuning / yield improvement / power reduction / programmable delay element (PDE) / / / / |
Reference Info. |
IEICE Tech. Rep., vol. 117, no. 455, VLD2017-107, pp. 109-114, Feb. 2018. |
Paper # |
VLD2017-107 |
Date of Issue |
2018-02-21 (VLD) |
ISSN |
Print edition: ISSN 0913-5685 Online edition: ISSN 2432-6380 |
Copyright and reproduction |
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034) |
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VLD2017-107 |
Conference Information |
Committee |
VLD HWS |
Conference Date |
2018-02-28 - 2018-03-02 |
Place (in Japanese) |
(See Japanese page) |
Place (in English) |
Okinawa Seinen Kaikan |
Topics (in Japanese) |
(See Japanese page) |
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Paper Information |
Registration To |
VLD |
Conference Code |
2018-02-VLD |
Language |
Japanese |
Title (in Japanese) |
(See Japanese page) |
Sub Title (in Japanese) |
(See Japanese page) |
Title (in English) |
Clustering for Reduction of Power Consumption and Area on Post-Silicon Delay Tuning |
Sub Title (in English) |
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Post-silicon delay tuning |
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yield improvement |
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power reduction |
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programmable delay element (PDE) |
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1st Author's Name |
Kota Muroi |
1st Author's Affiliation |
The University of Aizu (Univ. of Aizu) |
2nd Author's Name |
Yukihide Kohira |
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The University of Aizu (Univ. of Aizu) |
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Speaker |
Author-1 |
Date Time |
2018-03-01 09:50:00 |
Presentation Time |
25 minutes |
Registration for |
VLD |
Paper # |
VLD2017-107 |
Volume (vol) |
vol.117 |
Number (no) |
no.455 |
Page |
pp.109-114 |
#Pages |
6 |
Date of Issue |
2018-02-21 (VLD) |
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