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Paper Abstract and Keywords
Presentation 2018-11-26 13:30
[Poster Presentation] Experimental Performance Evaluation of Qubit Placement Techniques in Quantum Circuit Mapping
Toshinari Itoko, Takashi Imamichi (IBM)
Abstract (in Japanese) (See Japanese page) 
(in English) Current quantum computers have some restrictions such as noise, size, and qubit connectivity. In this paper, we focus on the qubit connectivity, i.e., we can apply CNOT gates to particular pairs of qubits. It is necessary to transform an input quantum circuit into an equivalent circuit to satisfy the qubit connectivity. The transformation is realized by specifying the initial qubit placement and adding extra CNOT gates in the middle of the circuit. In particular, we study the effects of the initial qubit placements empirically.
Keyword (in Japanese) (See Japanese page) 
(in English) quantum circuit / qubit placement / / / / / /  
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Conference Information
Committee QIT  
Conference Date 2018-11-26 - 2018-11-27 
Place (in Japanese) (See Japanese page) 
Place (in English) The University of Tokyo 
Topics (in Japanese) (See Japanese page) 
Topics (in English) Quantum Information 
Paper Information
Registration To QIT 
Conference Code 2018-11-QIT 
Language Japanese 
Title (in Japanese) (See Japanese page) 
Sub Title (in Japanese) (See Japanese page) 
Title (in English) Experimental Performance Evaluation of Qubit Placement Techniques in Quantum Circuit Mapping 
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Keyword(1) quantum circuit  
Keyword(2) qubit placement  
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1st Author's Name Toshinari Itoko  
1st Author's Affiliation IBM Research - Tokyo (IBM)
2nd Author's Name Takashi Imamichi  
2nd Author's Affiliation IBM Research - Tokyo (IBM)
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Speaker Author-1 
Date Time 2018-11-26 13:30:00 
Presentation Time 120 minutes 
Registration for QIT 
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