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Paper Abstract and Keywords
Presentation 2018-12-05 10:20
An FPGA implementation of Tri-state YOLOv2 using Intel OpenCL
Youki Sada, Masayuki Shimoda, Shimpei Sato, Hiroki Nakahara (titech) RECONF2018-35
Abstract (in Japanese) (See Japanese page) 
(in English) Since the convolutional neural network has a high-performance recognition accuracy,
it is expected to implement various applications on an embedded vision system.
An FPGA can calculate the inference algorithm with low-latency and low power consumption using a specific circuit.

In the paper, we propose a tri-state weight, which is a generalization of a low-precision and sparse~(pruning) for CNN weight, to reduce the operation cost and parameters of YOLO.
In the first layer, we set a weight ${-1,0,+1}$ as a ternary CNN, while in the other layers, we set a ${-w,0,+w}$ as a sparse weight CNN.
We apply an indirect memory access architecture to skip zero part and propose the weight parallel 2D convolutional circuit.
It can be applied to the AlexNet based CNN, which has different size kernels.
Thus, we design the AlexNet based YOLOv2 to reduce the number of layers toward low-latency computation.
In the experiment, the proposed tri-state scheme CNN reduces the 90% of weight parameter.
We implement the proposed tri-state weight YOLOv2 on a DE5aNet DDR4 board, which has the Intel Corp. Arria10 GX, by using Intel FPGA SDK for OpenCL.
It archived 429.0 frames per second (FPS) on a car and person recognition.
Compared with the Intel Corei7 7700, it was 203.3 times faster, and its performance per power efficiency was 190.0 times better.
Also, compared with the GeForce GTX 1070 GPU, it was 1.74 times faster, and its power performance efficiency was 2.63 times better.
Keyword (in Japanese) (See Japanese page) 
(in English) Intel OpenCL / Object Detection / Tristate YOLOv2 / Convolutional Neural Network / Ternary / Pruning / FPGA /  
Reference Info. IEICE Tech. Rep., vol. 118, no. 340, RECONF2018-35, pp. 7-12, Dec. 2018.
Paper # RECONF2018-35 
Date of Issue 2018-11-28 (RECONF) 
ISSN Online edition: ISSN 2432-6380
Copyright
and
reproduction
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034)
Download PDF RECONF2018-35

Conference Information
Committee VLD DC CPSY RECONF CPM ICD IE IPSJ-SLDM 
Conference Date 2018-12-05 - 2018-12-07 
Place (in Japanese) (See Japanese page) 
Place (in English) Satellite Campus Hiroshima 
Topics (in Japanese) (See Japanese page) 
Topics (in English) Design Gaia 2018 -New Field of VLSI Design- 
Paper Information
Registration To RECONF 
Conference Code 2018-12-VLD-DC-CPSY-RECONF-CPM-ICD-IE-SLDM-EMB-ARC 
Language Japanese 
Title (in Japanese) (See Japanese page) 
Sub Title (in Japanese) (See Japanese page) 
Title (in English) An FPGA implementation of Tri-state YOLOv2 using Intel OpenCL 
Sub Title (in English)  
Keyword(1) Intel OpenCL  
Keyword(2) Object Detection  
Keyword(3) Tristate YOLOv2  
Keyword(4) Convolutional Neural Network  
Keyword(5) Ternary  
Keyword(6) Pruning  
Keyword(7) FPGA  
Keyword(8)  
1st Author's Name Youki Sada  
1st Author's Affiliation Tokyo Institute of Technology (titech)
2nd Author's Name Masayuki Shimoda  
2nd Author's Affiliation Tokyo Institute of Technology (titech)
3rd Author's Name Shimpei Sato  
3rd Author's Affiliation Tokyo Institute of Technology (titech)
4th Author's Name Hiroki Nakahara  
4th Author's Affiliation Tokyo Institute of Technology (titech)
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Speaker Author-1 
Date Time 2018-12-05 10:20:00 
Presentation Time 25 minutes 
Registration for RECONF 
Paper # RECONF2018-35 
Volume (vol) vol.118 
Number (no) no.340 
Page pp.7-12 
#Pages
Date of Issue 2018-11-28 (RECONF) 


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