Paper Abstract and Keywords |
Presentation |
2019-01-18 11:05
Investigation of the Pulsed-IV Degradation Mechanism of GaN-HEMT under High Temperature Storage Tests Yasunori Tateno (Sumitomo Electric), Yasuyo Kurachi (Sumitomo Electric Device Innovations), Hiroshi Yamamoto, Takashi Nakabayashi (Sumitomo Electric) ED2018-82 MW2018-149 Link to ES Tech. Rep. Archives: ED2018-82 MW2018-149 |
Abstract |
(in Japanese) |
(See Japanese page) |
(in English) |
The purpose of this study is to investigate the physical mechanism of pulsed-IV degradation under high temperature storage tests. Using the measurements of the pulsed S-parameters immediately after the voltage stress was applied to the GaN-HEMT, we carried out the delay time analysis. As a result, we found that the so-called “virtual gate” region extended toward the drain electrode due to high temperature storage. From this result, we concluded that the electron tunnel injection probability at the gate edge increased and degraded the pulsed-IV characteristics. |
Keyword |
(in Japanese) |
(See Japanese page) |
(in English) |
delay time analysis / GaN-HEMT / high temperature storage test / pulsed I-V / pulsed S-parameters / / / |
Reference Info. |
IEICE Tech. Rep., vol. 118, no. 402, ED2018-82, pp. 71-74, Jan. 2019. |
Paper # |
ED2018-82 |
Date of Issue |
2019-01-10 (ED, MW) |
ISSN |
Print edition: ISSN 0913-5685 Online edition: ISSN 2432-6380 |
Copyright and reproduction |
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034) |
Download PDF |
ED2018-82 MW2018-149 Link to ES Tech. Rep. Archives: ED2018-82 MW2018-149 |
Conference Information |
Committee |
MW ED |
Conference Date |
2019-01-17 - 2019-01-18 |
Place (in Japanese) |
(See Japanese page) |
Place (in English) |
Hitachi, Central Research Lab. |
Topics (in Japanese) |
(See Japanese page) |
Topics (in English) |
Compound semiconductor, High speed and High frequency devices/Microwave technologies |
Paper Information |
Registration To |
ED |
Conference Code |
2019-01-MW-ED |
Language |
Japanese |
Title (in Japanese) |
(See Japanese page) |
Sub Title (in Japanese) |
(See Japanese page) |
Title (in English) |
Investigation of the Pulsed-IV Degradation Mechanism of GaN-HEMT under High Temperature Storage Tests |
Sub Title (in English) |
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Keyword(1) |
delay time analysis |
Keyword(2) |
GaN-HEMT |
Keyword(3) |
high temperature storage test |
Keyword(4) |
pulsed I-V |
Keyword(5) |
pulsed S-parameters |
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1st Author's Name |
Yasunori Tateno |
1st Author's Affiliation |
Sumitomo Electric Industries, Ltd. (Sumitomo Electric) |
2nd Author's Name |
Yasuyo Kurachi |
2nd Author's Affiliation |
Sumitomo Electric Device Innovations (Sumitomo Electric Device Innovations) |
3rd Author's Name |
Hiroshi Yamamoto |
3rd Author's Affiliation |
Sumitomo Electric Industries, Ltd. (Sumitomo Electric) |
4th Author's Name |
Takashi Nakabayashi |
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Sumitomo Electric Industries, Ltd. (Sumitomo Electric) |
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Speaker |
Author-1 |
Date Time |
2019-01-18 11:05:00 |
Presentation Time |
25 minutes |
Registration for |
ED |
Paper # |
ED2018-82, MW2018-149 |
Volume (vol) |
vol.118 |
Number (no) |
no.402(ED), no.403(MW) |
Page |
pp.71-74 |
#Pages |
4 |
Date of Issue |
2019-01-10 (ED, MW) |
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