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| Presentation | 2019-03-15 11:00 An Energy-Saving Digital-to-Time Converter for Ultra-Low-Power Digital PLLs Hongye Huang, Hanli Liu, Zheng Sun, Teruki Someya, Atsushi Shirane, Kenichi Okada (Tokyo Tech)  MW2018-172 ICD2018-116 Link to ES Tech. Rep. Archives: MW2018-172 ICD2018-116 |
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| Abstract | (in Japanese) | (See Japanese page) |
| (in English) | A digital-to-time converter (DTC) could be a critical part in a digital phase-locked loop (PLL). Comparing to other DTC structures, constant-slope DTCs could have better linearity and thus lead to better performance in PLLs. However, the original constant-slope DTC may cause energy waste. In this work, the truncated constant-slope DTC is introduced to cut down unnecessary charging and discharging phases. The truncated constant-slope DTC is implemented in 65nm CMOS process. In simulation, the power consumption of the truncated constant-slope DTC can be cut down 33%, while the noise and nonlinearity performance keep the same level as the conventional constant-slope DTC. | |
| Keyword | (in Japanese) | (See Japanese page) |
| (in English) | frequency synthesizer / mixed-signal circuit / low power design / digital-to-time converter (DTC) / phase-locked loop (PLL) / constant-slope / / | |
| Reference Info. | IEICE Tech. Rep., vol. 118, no. 507, ICD2018-116, pp. 87-91, March 2019. | |
| Paper # | ICD2018-116 | |
| Date of Issue | 2019-03-07 (MW, ICD) | |
| ISSN | Print edition: ISSN 0913-5685 Online edition: ISSN 2432-6380 | |
| Copyright and reproduction |
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034) | |
| Download PDF | MW2018-172 ICD2018-116 Link to ES Tech. Rep. Archives: MW2018-172 ICD2018-116 |
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| Conference Information | |
| Committee | MW ICD |
| Conference Date | 2019-03-14 - 2019-03-15 |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | Microwave Integrated Circuit/Microwave Technologies |
| Paper Information | |
| Registration To | ICD |
| Conference Code | 2019-03-MW-ICD |
| Language | English |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | An Energy-Saving Digital-to-Time Converter for Ultra-Low-Power Digital PLLs |
| Sub Title (in English) | |
| Keyword(1) | frequency synthesizer |
| Keyword(2) | mixed-signal circuit |
| Keyword(3) | low power design |
| Keyword(4) | digital-to-time converter (DTC) |
| Keyword(5) | phase-locked loop (PLL) |
| Keyword(6) | constant-slope |
| Keyword(7) | |
| Keyword(8) | |
| 1st Author's Name | Hongye Huang |
| 1st Author's Affiliation | Tokyo Institute of Technology (Tokyo Tech) |
| 2nd Author's Name | Hanli Liu |
| 2nd Author's Affiliation | Tokyo Institute of Technology (Tokyo Tech) |
| 3rd Author's Name | Zheng Sun |
| 3rd Author's Affiliation | Tokyo Institute of Technology (Tokyo Tech) |
| 4th Author's Name | Teruki Someya |
| 4th Author's Affiliation | Tokyo Institute of Technology (Tokyo Tech) |
| 5th Author's Name | Atsushi Shirane |
| 5th Author's Affiliation | Tokyo Institute of Technology (Tokyo Tech) |
| 6th Author's Name | Kenichi Okada |
| 6th Author's Affiliation | Tokyo Institute of Technology (Tokyo Tech) |
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| Speaker | Author-3 |
| Date Time | 2019-03-15 11:00:00 |
| Presentation Time | 25 minutes |
| Registration for | ICD |
| Paper # | MW2018-172, ICD2018-116 |
| Volume (vol) | vol.118 |
| Number (no) | no.506(MW), no.507(ICD) |
| Page | pp.87-91 |
| #Pages | 5 |
| Date of Issue | 2019-03-07 (MW, ICD) |
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