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| Presentation | 2019-03-17 16:10 Design of Vector Unit for AI Acceleration in Embedded Processor Yosuke Ide, Hiromi Suzuki, Yuki Mori, Nobuyuki Yamasaki (Keio Univ.)  CPSY2018-107 DC2018-89 |
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| Abstract | (in Japanese) | (See Japanese page) |
| (in English) | In recent years, AI is applied in wide range of fields. Its learning and recognition are based on Neural Network (NN), which are actively studied. Although for High-Performance Computing (HPC), GPU, FPGA or ASIC specialized to certain NN is proposed, it is not easy to apply them to embedded applications because of power consumption and area constraints. On the other hand, some embedded processors adopt vector units for multimedia application. In this study, extended vector load function and lower precision SIMD operation are added to vector units to accelerate convolution, which is executed in Convolutional Neural Network. | |
| Keyword | (in Japanese) | (See Japanese page) |
| (in English) | Embedded Processor / Vector Unit / Convolutionanl Neural Network / AI / / / / | |
| Reference Info. | IEICE Tech. Rep., vol. 118, no. 514, CPSY2018-107, pp. 167-172, March 2019. | |
| Paper # | CPSY2018-107 | |
| Date of Issue | 2019-03-10 (CPSY, DC) | |
| ISSN | Online edition: ISSN 2432-6380 | |
| Copyright and reproduction |
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034) | |
| Download PDF | CPSY2018-107 DC2018-89 |
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| Conference Information | |
| Committee | CPSY DC IPSJ-SLDM IPSJ-EMB IPSJ-ARC |
| Conference Date | 2019-03-17 - 2019-03-18 |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | Nishinoomote City Hall (Tanega-shima) |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | ETNET2019 |
| Paper Information | |
| Registration To | CPSY |
| Conference Code | 2019-03-CPSY-DC-SLDM-EMB-ARC |
| Language | Japanese |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | Design of Vector Unit for AI Acceleration in Embedded Processor |
| Sub Title (in English) | |
| Keyword(1) | Embedded Processor |
| Keyword(2) | Vector Unit |
| Keyword(3) | Convolutionanl Neural Network |
| Keyword(4) | AI |
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| 1st Author's Name | Yosuke Ide |
| 1st Author's Affiliation | Keio University (Keio Univ.) |
| 2nd Author's Name | Hiromi Suzuki |
| 2nd Author's Affiliation | Keio University (Keio Univ.) |
| 3rd Author's Name | Yuki Mori |
| 3rd Author's Affiliation | Keio University (Keio Univ.) |
| 4th Author's Name | Nobuyuki Yamasaki |
| 4th Author's Affiliation | Keio University (Keio Univ.) |
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| Speaker | Author-1 |
| Date Time | 2019-03-17 16:10:00 |
| Presentation Time | 20 minutes |
| Registration for | CPSY |
| Paper # | CPSY2018-107, DC2018-89 |
| Volume (vol) | vol.118 |
| Number (no) | no.514(CPSY), no.515(DC) |
| Page | pp.167-172 |
| #Pages | 6 |
| Date of Issue | 2019-03-10 (CPSY, DC) |
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