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| Presentation | 2019-05-15 15:25 SRAM-Based Synthesis for Multi-Output Gates Xingming Le, Amir Masoud Gharehbaghi, Masahiro Fujita (The Univ. of Tokyo)  VLD2019-4 |
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| Abstract | (in Japanese) | (See Japanese page) |
| (in English) | Conventionally a circuit is represented as a network of single-output gates. In this paper, we propose an implementation with SRAM for multiple-output gates. Due to SRAM's multi-output nature and SRAM cell's compact structure, using multi-output gates to represent the circuit may become good for area efficiency if synthesized in an ideal way. We will compare the traditional implementation and SRAM-based implementation of look-up tables(LUTs) by modeling, and perform the synthesis by merging the nodes with several methods. Finally, we estimate the possibility of area reduction based on the experimental results. | |
| Keyword | (in Japanese) | (See Japanese page) |
| (in English) | multi-output gate / SRAM / LUT / logic synthesis / / / / | |
| Reference Info. | IEICE Tech. Rep., vol. 119, no. 25, VLD2019-4, pp. 25-30, May 2019. | |
| Paper # | VLD2019-4 | |
| Date of Issue | 2019-05-08 (VLD) | |
| ISSN | Print edition: ISSN 0913-5685 Online edition: ISSN 2432-6380 | |
| Copyright and reproduction |
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034) | |
| Download PDF | VLD2019-4 |
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| Conference Information | |
| Committee | VLD IPSJ-SLDM |
| Conference Date | 2019-05-15 - 2019-05-15 |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | Ookayama Campus, Tokyo Institute of Technology |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | System Design, etc. |
| Paper Information | |
| Registration To | VLD |
| Conference Code | 2019-05-VLD-SLDM |
| Language | English |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | SRAM-Based Synthesis for Multi-Output Gates |
| Sub Title (in English) | |
| Keyword(1) | multi-output gate |
| Keyword(2) | SRAM |
| Keyword(3) | LUT |
| Keyword(4) | logic synthesis |
| Keyword(5) | |
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| 1st Author's Name | Xingming Le |
| 1st Author's Affiliation | The University of Tokyo (The Univ. of Tokyo) |
| 2nd Author's Name | Amir Masoud Gharehbaghi |
| 2nd Author's Affiliation | The University of Tokyo (The Univ. of Tokyo) |
| 3rd Author's Name | Masahiro Fujita |
| 3rd Author's Affiliation | The University of Tokyo (The Univ. of Tokyo) |
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| Speaker | Author-1 |
| Date Time | 2019-05-15 15:25:00 |
| Presentation Time | 25 minutes |
| Registration for | VLD |
| Paper # | VLD2019-4 |
| Volume (vol) | vol.119 |
| Number (no) | no.25 |
| Page | pp.25-30 |
| #Pages | 6 |
| Date of Issue | 2019-05-08 (VLD) |
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