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Paper Abstract and Keywords
Presentation 2019-06-13 11:20
A random number generation method for hardware implemented neural networks
Sansei Hori, Hakaru Tamukoh (Kyushu Inst. of Tech.) SIS2019-1
Abstract (in Japanese) (See Japanese page) 
(in English) This study proposes a hardware oriented random number generation method to implement a stochastically neural networks such as restricted Boltzmann machines (RBMs) into field programmable gate arrays (FPGAs). Generally, hardware oriented random number generators (RNGs) employ linear feedback shift registers (LFSRs). However, the RNGs require considerable circuit resources. Therefore, it is difficult to implement a large scale of neural network such as deep neural networks (DNNs) with the RNGs. In the proposed method, we employ the underflow bits from calculations by fixed-point numbers instead of the RNGs to reduce the circuit resources.
In this report, we implemented an RBM which employed the proposed method into a software environment and trained the MNIST dataset to evaluate it.
Keyword (in Japanese) (See Japanese page) 
(in English) Random number generators / Restricted Boltzmann machines / Digital hardware / FPGA / / / /  
Reference Info. IEICE Tech. Rep., vol. 119, no. 78, SIS2019-1, pp. 1-4, June 2019.
Paper # SIS2019-1 
Date of Issue 2019-06-06 (SIS) 
ISSN Print edition: ISSN 0913-5685    Online edition: ISSN 2432-6380
Copyright
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reproduction
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034)
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Conference Information
Committee SIS IPSJ-AVM ITE-3DMT  
Conference Date 2019-06-13 - 2019-06-14 
Place (in Japanese) (See Japanese page) 
Place (in English) Fukue Culture Center 
Topics (in Japanese) (See Japanese page) 
Topics (in English) Intelligent Multimedia Systems, Applied Enbedded Systems, Three-Dimensional Image Technology (3DIT), etc. 
Paper Information
Registration To SIS 
Conference Code 2019-06-SIS-AVM-3DIT 
Language Japanese 
Title (in Japanese) (See Japanese page) 
Sub Title (in Japanese) (See Japanese page) 
Title (in English) A random number generation method for hardware implemented neural networks 
Sub Title (in English)  
Keyword(1) Random number generators  
Keyword(2) Restricted Boltzmann machines  
Keyword(3) Digital hardware  
Keyword(4) FPGA  
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1st Author's Name Sansei Hori  
1st Author's Affiliation Kyushu Institute of Technology (Kyushu Inst. of Tech.)
2nd Author's Name Hakaru Tamukoh  
2nd Author's Affiliation Kyushu Institute of Technology (Kyushu Inst. of Tech.)
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Speaker Author-1 
Date Time 2019-06-13 11:20:00 
Presentation Time 20 minutes 
Registration for SIS 
Paper # SIS2019-1 
Volume (vol) vol.119 
Number (no) no.78 
Page pp.1-4 
#Pages
Date of Issue 2019-06-06 (SIS) 


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