Paper Abstract and Keywords |
Presentation |
2019-07-23 14:25
Side Channel Security of an FPGA Pairing Implementation with Pipelined Modular Multiplier Mitsufumi Yamazaki, Junichi Sakamoto, Yuta Okuaki, Tsutomu Matsumoto (YNU) ISEC2019-29 SITE2019-23 BioX2019-21 HWS2019-24 ICSS2019-27 EMM2019-32 |
Abstract |
(in Japanese) |
(See Japanese page) |
(in English) |
Since bilinear pairing is useful in realizing advanced cryptography, side channel security evaluation of its high-speed hardware implementation is an important issue. We implemented on the SAKURA-X board the main part extracted from the fastest FPGA implementation that calculates the optimal Ate pairing on a BN curve using a pipelined modular multiplier. We performed side-channel attack experiments on this implementation and discussed side-channel security of the original pairing implementation. |
Keyword |
(in Japanese) |
(See Japanese page) |
(in English) |
Bilinear pairing / advanced cryptography / optimal Ate pairing / pipelined modular multiplier / FPGA pairing implementation / side-channel attack / side-channel security / |
Reference Info. |
IEICE Tech. Rep., vol. 119, no. 143, HWS2019-24, pp. 151-156, July 2019. |
Paper # |
HWS2019-24 |
Date of Issue |
2019-07-16 (ISEC, SITE, BioX, HWS, ICSS, EMM) |
ISSN |
Print edition: ISSN 0913-5685 Online edition: ISSN 2432-6380 |
Copyright and reproduction |
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034) |
Download PDF |
ISEC2019-29 SITE2019-23 BioX2019-21 HWS2019-24 ICSS2019-27 EMM2019-32 |
Conference Information |
Committee |
ISEC SITE ICSS EMM HWS BioX IPSJ-CSEC IPSJ-SPT |
Conference Date |
2019-07-23 - 2019-07-24 |
Place (in Japanese) |
(See Japanese page) |
Place (in English) |
Kochi University of Technology |
Topics (in Japanese) |
(See Japanese page) |
Topics (in English) |
Security, etc. |
Paper Information |
Registration To |
HWS |
Conference Code |
2019-07-ISEC-SITE-ICSS-EMM-HWS-BioX-CSEC-SPT |
Language |
Japanese |
Title (in Japanese) |
(See Japanese page) |
Sub Title (in Japanese) |
(See Japanese page) |
Title (in English) |
Side Channel Security of an FPGA Pairing Implementation with Pipelined Modular Multiplier |
Sub Title (in English) |
|
Keyword(1) |
Bilinear pairing |
Keyword(2) |
advanced cryptography |
Keyword(3) |
optimal Ate pairing |
Keyword(4) |
pipelined modular multiplier |
Keyword(5) |
FPGA pairing implementation |
Keyword(6) |
side-channel attack |
Keyword(7) |
side-channel security |
Keyword(8) |
|
1st Author's Name |
Mitsufumi Yamazaki |
1st Author's Affiliation |
Yokohama National University (YNU) |
2nd Author's Name |
Junichi Sakamoto |
2nd Author's Affiliation |
Yokohama National University (YNU) |
3rd Author's Name |
Yuta Okuaki |
3rd Author's Affiliation |
Yokohama National University (YNU) |
4th Author's Name |
Tsutomu Matsumoto |
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Yokohama National University (YNU) |
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Speaker |
Author-1 |
Date Time |
2019-07-23 14:25:00 |
Presentation Time |
25 minutes |
Registration for |
HWS |
Paper # |
ISEC2019-29, SITE2019-23, BioX2019-21, HWS2019-24, ICSS2019-27, EMM2019-32 |
Volume (vol) |
vol.119 |
Number (no) |
no.140(ISEC), no.141(SITE), no.142(BioX), no.143(HWS), no.144(ICSS), no.145(EMM) |
Page |
pp.151-156 |
#Pages |
6 |
Date of Issue |
2019-07-16 (ISEC, SITE, BioX, HWS, ICSS, EMM) |