講演抄録/キーワード |
講演名 |
2020-01-17 13:15
[ポスター講演]A Routing Method with Wire Length Matching for RSFQ Logic Circuits Using Thin PTLs ○Kei Kitamura(Kyoto Univ)・Kazuyoshi Takagi(Mie Univ)・Naofumi Takagi(Kyoto Univ) SCE2019-35 エレソ技報アーカイブへのリンク:SCE2019-35 |
抄録 |
(和) |
(まだ登録されていません) |
(英) |
A routing method with wire length matching using thin PTLs for RSFQ circuits is proposed. For AIST-ADP2 fabrication technology for thin PTL technology is under development aiming at wiring four PTLs in a unit placement grid. The proposed method is supposed to use that technology. Two in the middle of four wiring tracks are reserved to be used for wire length matching and extension of routes are performed on the reserved wiring tracks after connecting placed gates. The routes can be extended without using relatively large via-holes by using the reserved wiring tracks, and therefore wire length matching can be done while using routing resources effectively. |
キーワード |
(和) |
/ / / / / / / |
(英) |
RSFQ logic circuits / Passive Transmission Lines / Routing / Wire-length matching / / / / |
文献情報 |
信学技報, vol. 119, no. 369, SCE2019-35, pp. 23-25, 2020年1月. |
資料番号 |
SCE2019-35 |
発行日 |
2020-01-09 (SCE) |
ISSN |
Print edition: ISSN 0913-5685 Online edition: ISSN 2432-6380 |
著作権に ついて |
技術研究報告に掲載された論文の著作権は電子情報通信学会に帰属します.(許諾番号:10GA0019/12GB0052/13GB0056/17GB0034/18GB0034) |
PDFダウンロード |
SCE2019-35 エレソ技報アーカイブへのリンク:SCE2019-35 |