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| Presentation | 2020-01-17 13:15 [Poster Presentation] A Routing Method with Wire Length Matching for RSFQ Logic Circuits Using Thin PTLs Kei Kitamura (Kyoto Univ), Kazuyoshi Takagi (Mie Univ), Naofumi Takagi (Kyoto Univ)  SCE2019-35 Link to ES Tech. Rep. Archives: SCE2019-35 |
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| Abstract | (in Japanese) | (See Japanese page) |
| (in English) | A routing method with wire length matching using thin PTLs for RSFQ circuits is proposed. For AIST-ADP2 fabrication technology for thin PTL technology is under development aiming at wiring four PTLs in a unit placement grid. The proposed method is supposed to use that technology. Two in the middle of four wiring tracks are reserved to be used for wire length matching and extension of routes are performed on the reserved wiring tracks after connecting placed gates. The routes can be extended without using relatively large via-holes by using the reserved wiring tracks, and therefore wire length matching can be done while using routing resources effectively. | |
| Keyword | (in Japanese) | (See Japanese page) |
| (in English) | RSFQ logic circuits / Passive Transmission Lines / Routing / Wire-length matching / / / / | |
| Reference Info. | IEICE Tech. Rep., vol. 119, no. 369, SCE2019-35, pp. 23-25, Jan. 2020. | |
| Paper # | SCE2019-35 | |
| Date of Issue | 2020-01-09 (SCE) | |
| ISSN | Print edition: ISSN 0913-5685 Online edition: ISSN 2432-6380 | |
| Copyright and reproduction |
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034) | |
| Download PDF | SCE2019-35 Link to ES Tech. Rep. Archives: SCE2019-35 |
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| Conference Information | |
| Committee | SCE |
| Conference Date | 2020-01-16 - 2020-01-17 |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | |
| Paper Information | |
| Registration To | SCE |
| Conference Code | 2020-01-SCE |
| Language | English |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | A Routing Method with Wire Length Matching for RSFQ Logic Circuits Using Thin PTLs |
| Sub Title (in English) | |
| Keyword(1) | RSFQ logic circuits |
| Keyword(2) | Passive Transmission Lines |
| Keyword(3) | Routing |
| Keyword(4) | Wire-length matching |
| Keyword(5) | |
| Keyword(6) | |
| Keyword(7) | |
| Keyword(8) | |
| 1st Author's Name | Kei Kitamura |
| 1st Author's Affiliation | Kyoto University (Kyoto Univ) |
| 2nd Author's Name | Kazuyoshi Takagi |
| 2nd Author's Affiliation | Mie University (Mie Univ) |
| 3rd Author's Name | Naofumi Takagi |
| 3rd Author's Affiliation | Kyoto University (Kyoto Univ) |
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| Speaker | Author-1 |
| Date Time | 2020-01-17 13:15:00 |
| Presentation Time | 135 minutes |
| Registration for | SCE |
| Paper # | SCE2019-35 |
| Volume (vol) | vol.119 |
| Number (no) | no.369 |
| Page | pp.23-25 |
| #Pages | 3 |
| Date of Issue | 2020-01-09 (SCE) |
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