IEICE Technical Committee Submission System
Conference Paper's Information
Online Proceedings
[Sign in]
Tech. Rep. Archives
 Go Top Page Go Previous   [Japanese] / [English] 

Paper Abstract and Keywords
Presentation 2020-01-22 17:45
An FPGA Implementation of Monocular Depth Estimation
Youki Sada, Masayuki Shimoda, Shimpei Sato, Hiroki Nakahara (titech) VLD2019-66 CPSY2019-64 RECONF2019-56
Abstract (in Japanese) (See Japanese page) 
(in English) Among a lot of image recognition applications, Convolutional Neural Network (CNN) has gained high accuracy and increasing interest. It is rapidly required to implement a real-time and energy-efficient depth estimation in embedded systems. Because depth estimation is important to understand the scene and it is required on many applications such as robotics, 3D modeling and driving automation systems. The monocular depth estimation estimates the depth from a single RGB image. And it is paid attention due to the reliability of a monocular RGB camera, low cost and its small requirement of hardware resource. Moreover, there is the possibility to replace an expensive depth sensor such as a LiDAR or a stereo camera into the general RGB camera.
We choose the CNN-based monocular depth estimation since CNN schemes are able to realize accurate and dense estimation. However, CNN schemes require a massive amount of multiplications and it makes difficult to implement an accurate system under limited device resources. To handle this, we adopt 8-bit quantization and weight pruning in order to implement an FPGA with high inference speed. Then, our CNN-based estimation is demonstrated on OpenVINO Starter Kit due to real-time requirements and energy-efficiency. Because GPUs consume too much of power and CPUs are too slow due to the numerous operations in the CNN, FPGA system is better performance per power using a custom design for the depth estimation.
Keyword (in Japanese) (See Japanese page) 
(in English) Convolutional Neural Network / FPGA / Monocular Depth Estimation / Quantization / Pruning / / /  
Reference Info. IEICE Tech. Rep., vol. 119, no. 373, RECONF2019-56, pp. 73-78, Jan. 2020.
Paper # RECONF2019-56 
Date of Issue 2020-01-15 (VLD, CPSY, RECONF) 
ISSN Print edition: ISSN 0913-5685    Online edition: ISSN 2432-6380
Copyright
and
reproduction
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034)
Download PDF VLD2019-66 CPSY2019-64 RECONF2019-56

Conference Information
Committee IPSJ-SLDM RECONF VLD CPSY IPSJ-ARC  
Conference Date 2020-01-22 - 2020-01-24 
Place (in Japanese) (See Japanese page) 
Place (in English) Raiosha, Hiyoshi Campus, Keio University 
Topics (in Japanese) (See Japanese page) 
Topics (in English) FPGA Applications, etc. 
Paper Information
Registration To RECONF 
Conference Code 2020-01-SLDM-RECONF-VLD-CPSY-ARC 
Language Japanese 
Title (in Japanese) (See Japanese page) 
Sub Title (in Japanese) (See Japanese page) 
Title (in English) An FPGA Implementation of Monocular Depth Estimation 
Sub Title (in English)  
Keyword(1) Convolutional Neural Network  
Keyword(2) FPGA  
Keyword(3) Monocular Depth Estimation  
Keyword(4) Quantization  
Keyword(5) Pruning  
Keyword(6)  
Keyword(7)  
Keyword(8)  
1st Author's Name Youki Sada  
1st Author's Affiliation Tokyo Institute of Technology (titech)
2nd Author's Name Masayuki Shimoda  
2nd Author's Affiliation Tokyo Institute of Technology (titech)
3rd Author's Name Shimpei Sato  
3rd Author's Affiliation Tokyo Institute of Technology (titech)
4th Author's Name Hiroki Nakahara  
4th Author's Affiliation Tokyo Institute of Technology (titech)
5th Author's Name  
5th Author's Affiliation ()
6th Author's Name  
6th Author's Affiliation ()
7th Author's Name  
7th Author's Affiliation ()
8th Author's Name  
8th Author's Affiliation ()
9th Author's Name  
9th Author's Affiliation ()
10th Author's Name  
10th Author's Affiliation ()
11th Author's Name  
11th Author's Affiliation ()
12th Author's Name  
12th Author's Affiliation ()
13th Author's Name  
13th Author's Affiliation ()
14th Author's Name  
14th Author's Affiliation ()
15th Author's Name  
15th Author's Affiliation ()
16th Author's Name  
16th Author's Affiliation ()
17th Author's Name  
17th Author's Affiliation ()
18th Author's Name  
18th Author's Affiliation ()
19th Author's Name  
19th Author's Affiliation ()
20th Author's Name  
20th Author's Affiliation ()
Speaker Author-1 
Date Time 2020-01-22 17:45:00 
Presentation Time 25 minutes 
Registration for RECONF 
Paper # VLD2019-66, CPSY2019-64, RECONF2019-56 
Volume (vol) vol.119 
Number (no) no.371(VLD), no.372(CPSY), no.373(RECONF) 
Page pp.73-78 
#Pages
Date of Issue 2020-01-15 (VLD, CPSY, RECONF) 


[Return to Top Page]

[Return to IEICE Web Page]


The Institute of Electronics, Information and Communication Engineers (IEICE), Japan