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| Presentation | 2020-02-26 14:35 Power Analysis for Logic Area of LSI Including Memory Area Yuya Kodama, Kohei Miyase, Daiki Takafuji, Xiaoqing Wen, Seiji Kajihara (Kyutech)  DC2019-93 |
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| Abstract | (in Japanese) | (See Japanese page) |
| (in English) | Power consumption during LSI testing is higher than functional mode. Excessive IR-drop causes excessive delay, resulting in over-testing in particular for at-speed testing. Over-testing is directly related to yield loss. Therefore, test power reduction and efficient power analysis is required. Since excessive IR-drop does not occur in whole area of LSI, locating an area with high IR-drop is very important. Although an LSI includes memory design in general, academic version of benchmark logic circuits does not have memories.In this work, we analyze power consumption for a logic part of LSI including memory design. | |
| Keyword | (in Japanese) | (See Japanese page) |
| (in English) | at-speed testing / test power / IR-drop / over-testing / power analysis / / / | |
| Reference Info. | IEICE Tech. Rep., vol. 119, no. 420, DC2019-93, pp. 43-48, Feb. 2020. | |
| Paper # | DC2019-93 | |
| Date of Issue | 2020-02-19 (DC) | |
| ISSN | Online edition: ISSN 2432-6380 | |
| Copyright and reproduction |
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034) | |
| Download PDF | DC2019-93 |
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| Conference Information | |
| Committee | DC |
| Conference Date | 2020-02-26 - 2020-02-26 |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | |
| Paper Information | |
| Registration To | DC |
| Conference Code | 2020-02-DC |
| Language | Japanese |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | Power Analysis for Logic Area of LSI Including Memory Area |
| Sub Title (in English) | |
| Keyword(1) | at-speed testing |
| Keyword(2) | test power |
| Keyword(3) | IR-drop |
| Keyword(4) | over-testing |
| Keyword(5) | power analysis |
| Keyword(6) | |
| Keyword(7) | |
| Keyword(8) | |
| 1st Author's Name | Yuya Kodama |
| 1st Author's Affiliation | Kyushu Institute of Technology (Kyutech) |
| 2nd Author's Name | Kohei Miyase |
| 2nd Author's Affiliation | Kyushu Institute of Technology (Kyutech) |
| 3rd Author's Name | Daiki Takafuji |
| 3rd Author's Affiliation | Kyushu Institute of Technology (Kyutech) |
| 4th Author's Name | Xiaoqing Wen |
| 4th Author's Affiliation | Kyushu Institute of Technology (Kyutech) |
| 5th Author's Name | Seiji Kajihara |
| 5th Author's Affiliation | Kyushu Institute of Technology (Kyutech) |
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| Speaker | Author-1 |
| Date Time | 2020-02-26 14:35:00 |
| Presentation Time | 25 minutes |
| Registration for | DC |
| Paper # | DC2019-93 |
| Volume (vol) | vol.119 |
| Number (no) | no.420 |
| Page | pp.43-48 |
| #Pages | 6 |
| Date of Issue | 2020-02-19 (DC) |
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