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Paper Abstract and Keywords
Presentation 2020-03-04 11:20
A Study of Arithmetic-Oriented Application Implementations for Via-Switch FPGA
Takashi Imagawa (Ritsumeikan Univ.), Yu Jaehoon (Tokyo Tech), Masanori Hashimoto (Osaka Univ.), Hiroyuki Ochi (Ritsumeikan Univ.) VLD2019-98 HWS2019-71
Abstract (in Japanese) (See Japanese page) 
(in English) Via-Switch FPGAs have different features from conventional SRAM-based FPGAs. It is necessary to build the application circuit implementation methodology and technology mapping algorithm in consideration of their difference. In this paper, we compare typical arithmetic-operation-based application circuits, such as matrix multiplication and FFT, implemented by different technology mapping policies, and report the differences in the number of computation resources and the number of their fan-outs.
Keyword (in Japanese) (See Japanese page) 
(in English) Via-Switch FPGA / technology mapping / / / / / /  
Reference Info. IEICE Tech. Rep., vol. 119, no. 443, VLD2019-98, pp. 25-29, March 2020.
Paper # VLD2019-98 
Date of Issue 2020-02-26 (VLD, HWS) 
ISSN Print edition: ISSN 0913-5685    Online edition: ISSN 2432-6380
Copyright
and
reproduction
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034)
Download PDF VLD2019-98 HWS2019-71

Conference Information
Committee HWS VLD  
Conference Date 2020-03-04 - 2020-03-07 
Place (in Japanese) (See Japanese page) 
Place (in English) Okinawa Ken Seinen Kaikan 
Topics (in Japanese) (See Japanese page) 
Topics (in English) Design Technology for System-on-Silicon, Hardware Security, etc. 
Paper Information
Registration To VLD 
Conference Code 2020-03-HWS-VLD 
Language Japanese 
Title (in Japanese) (See Japanese page) 
Sub Title (in Japanese) (See Japanese page) 
Title (in English) A Study of Arithmetic-Oriented Application Implementations for Via-Switch FPGA 
Sub Title (in English)  
Keyword(1) Via-Switch FPGA  
Keyword(2) technology mapping  
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1st Author's Name Takashi Imagawa  
1st Author's Affiliation Ritsumeikan University (Ritsumeikan Univ.)
2nd Author's Name Yu Jaehoon  
2nd Author's Affiliation Tokyo Institute of Technology (Tokyo Tech)
3rd Author's Name Masanori Hashimoto  
3rd Author's Affiliation Osaka University (Osaka Univ.)
4th Author's Name Hiroyuki Ochi  
4th Author's Affiliation Ritsumeikan University (Ritsumeikan Univ.)
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Speaker Author-1 
Date Time 2020-03-04 11:20:00 
Presentation Time 25 minutes 
Registration for VLD 
Paper # VLD2019-98, HWS2019-71 
Volume (vol) vol.119 
Number (no) no.443(VLD), no.444(HWS) 
Page pp.25-29 
#Pages
Date of Issue 2020-02-26 (VLD, HWS) 


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