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| Paper Abstract and Keywords | ||
| Presentation | 2020-03-04 13:25 A Study of Dynamic Power Optimization by Latch Insertion for Asynchronous RTL Models Shogo Semba, Hiroshi Saito (UoA)  VLD2019-100 HWS2019-73 |
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| Abstract | (in Japanese) | (See Japanese page) |
| (in English) | In this paper, we propose a dynamic power optimization method by latch insertion for asynchronous RTL models. In data-paths of the asynchronous RTL model, the proposed method inserts latches before combinational circuits to prevent the unnecessary operations. We also study a latch insertion by considering critical path delays to satisfy latency constraint. In the experiment, we applied the proposed method for three benchmarks and evaluated the reduction effect of dynamic power consumption. Compared to synchronous circuits with traditional operand isolations, the proposed latch insertion method reduced the dynamic power consumption by 28.2% on the average. On the other hand, the latch insertion method by considering critical path delays reduced the dynamic power consumption by 11.5% on the average. | |
| Keyword | (in Japanese) | (See Japanese page) |
| (in English) | asynchronous circuits / RTL / dynamic power consumption / operand isolation / / / / | |
| Reference Info. | IEICE Tech. Rep., vol. 119, no. 443, VLD2019-100, pp. 37-42, March 2020. | |
| Paper # | VLD2019-100 | |
| Date of Issue | 2020-02-26 (VLD, HWS) | |
| ISSN | Print edition: ISSN 0913-5685 Online edition: ISSN 2432-6380 | |
| Copyright and reproduction |
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034) | |
| Download PDF | VLD2019-100 HWS2019-73 |
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| Conference Information | |
| Committee | HWS VLD |
| Conference Date | 2020-03-04 - 2020-03-07 |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | Okinawa Ken Seinen Kaikan |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | Design Technology for System-on-Silicon, Hardware Security, etc. |
| Paper Information | |
| Registration To | VLD |
| Conference Code | 2020-03-HWS-VLD |
| Language | Japanese |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | A Study of Dynamic Power Optimization by Latch Insertion for Asynchronous RTL Models |
| Sub Title (in English) | |
| Keyword(1) | asynchronous circuits |
| Keyword(2) | RTL |
| Keyword(3) | dynamic power consumption |
| Keyword(4) | operand isolation |
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| 1st Author's Name | Shogo Semba |
| 1st Author's Affiliation | The University of Aizu (UoA) |
| 2nd Author's Name | Hiroshi Saito |
| 2nd Author's Affiliation | The University of Aizu (UoA) |
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| Speaker | Author-1 |
| Date Time | 2020-03-04 13:25:00 |
| Presentation Time | 25 minutes |
| Registration for | VLD |
| Paper # | VLD2019-100, HWS2019-73 |
| Volume (vol) | vol.119 |
| Number (no) | no.443(VLD), no.444(HWS) |
| Page | pp.37-42 |
| #Pages | 6 |
| Date of Issue | 2020-02-26 (VLD, HWS) |
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