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Paper Abstract and Keywords
Presentation 2020-03-04 10:30
An EVBDD-based Design Verification for Elementary Function Generators
Hiroto Fukuhara, Shinobu Nagayama, Masato Inagi, Shin'ichi Wakabayashi (HCU) VLD2019-96 HWS2019-69
Abstract (in Japanese) (See Japanese page) 
(in English) This paper proposes a design verification based on edge-valued binary decision
diagrams (EVBDDs) for elementary function generators.
In the proposed method, target circuits are compactly represetend by EVBDDs,
and the maximum errors of the circuits are computed by comparing with EVBDDs
representing design specifications (i.e., reference models).
We can formally verify elementary function generators by making sure if the
maximum errors are tolerable.
To efficiently generate EVBDDs from the target circuits, this paper also
presents some arithmetic operation algorithms for EVBDDs that corresponds
to arithmetic operations in the circuits.
Experimental results show the efficiency of the proposed verification method.
Keyword (in Japanese) (See Japanese page) 
(in English) EVBDD / design verification of elementary function generators / formal verification / graph operations / / / /  
Reference Info. IEICE Tech. Rep., vol. 119, no. 443, VLD2019-96, pp. 13-18, March 2020.
Paper # VLD2019-96 
Date of Issue 2020-02-26 (VLD, HWS) 
ISSN Print edition: ISSN 0913-5685    Online edition: ISSN 2432-6380
Copyright
and
reproduction
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034)
Download PDF VLD2019-96 HWS2019-69

Conference Information
Committee HWS VLD  
Conference Date 2020-03-04 - 2020-03-07 
Place (in Japanese) (See Japanese page) 
Place (in English) Okinawa Ken Seinen Kaikan 
Topics (in Japanese) (See Japanese page) 
Topics (in English) Design Technology for System-on-Silicon, Hardware Security, etc. 
Paper Information
Registration To VLD 
Conference Code 2020-03-HWS-VLD 
Language Japanese 
Title (in Japanese) (See Japanese page) 
Sub Title (in Japanese) (See Japanese page) 
Title (in English) An EVBDD-based Design Verification for Elementary Function Generators 
Sub Title (in English)  
Keyword(1) EVBDD  
Keyword(2) design verification of elementary function generators  
Keyword(3) formal verification  
Keyword(4) graph operations  
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1st Author's Name Hiroto Fukuhara  
1st Author's Affiliation Hiroshima City University (HCU)
2nd Author's Name Shinobu Nagayama  
2nd Author's Affiliation Hiroshima City University (HCU)
3rd Author's Name Masato Inagi  
3rd Author's Affiliation Hiroshima City University (HCU)
4th Author's Name Shin'ichi Wakabayashi  
4th Author's Affiliation Hiroshima City University (HCU)
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Speaker Author-1 
Date Time 2020-03-04 10:30:00 
Presentation Time 25 minutes 
Registration for VLD 
Paper # VLD2019-96, HWS2019-69 
Volume (vol) vol.119 
Number (no) no.443(VLD), no.444(HWS) 
Page pp.13-18 
#Pages
Date of Issue 2020-02-26 (VLD, HWS) 


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