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| Presentation | 2020-03-06 11:40 1 Bit Error Tolerance Considering Delay of the Protocol for Reticent Sender Cooperated with Aggressively Speaking Receiver Yuki Ito, Yoshiaki Kitaguchi, Katsunori Yamaoka (Tokyo Tech)  IN2019-123 |
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| Abstract | (in Japanese) | (See Japanese page) |
| (in English) | We have proposed two methods of 1 bit error tolerance of the protocol for reticent sender cooperated with aggressively speaking receiver which is effective in the asymmetric channel. One is the method by error detection and resend, the other is by error correction code. Former can reduce the number of bits sent from user, but causes large delay. On the other hand, later can reduce its delay, but increases the number of bits. We show trade-off relation between two parameter, the number of bits and delay, by theoretical analysis. |
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| Keyword | (in Japanese) | (See Japanese page) |
| (in English) | communication protocol / asymmetric channel / error correction / delay / throughput / / / | |
| Reference Info. | IEICE Tech. Rep., vol. 119, no. 461, IN2019-123, pp. 267-272, March 2020. | |
| Paper # | IN2019-123 | |
| Date of Issue | 2020-02-27 (IN) | |
| ISSN | Online edition: ISSN 2432-6380 | |
| Copyright and reproduction |
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034) | |
| Download PDF | IN2019-123 |
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| Conference Information | |
| Committee | NS IN |
| Conference Date | 2020-03-05 - 2020-03-06 |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | Royal Hotel Okinawa Zanpa-Misaki |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | General |
| Paper Information | |
| Registration To | IN |
| Conference Code | 2020-03-NS-IN |
| Language | Japanese |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | 1 Bit Error Tolerance Considering Delay of the Protocol for Reticent Sender Cooperated with Aggressively Speaking Receiver |
| Sub Title (in English) | |
| Keyword(1) | communication protocol |
| Keyword(2) | asymmetric channel |
| Keyword(3) | error correction |
| Keyword(4) | delay |
| Keyword(5) | throughput |
| Keyword(6) | |
| Keyword(7) | |
| Keyword(8) | |
| 1st Author's Name | Yuki Ito |
| 1st Author's Affiliation | Tokyo Institute of Technology (Tokyo Tech) |
| 2nd Author's Name | Yoshiaki Kitaguchi |
| 2nd Author's Affiliation | Tokyo Institute of Technology (Tokyo Tech) |
| 3rd Author's Name | Katsunori Yamaoka |
| 3rd Author's Affiliation | Tokyo Institute of Technology (Tokyo Tech) |
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| Speaker | Author-1 |
| Date Time | 2020-03-06 11:40:00 |
| Presentation Time | 20 minutes |
| Registration for | IN |
| Paper # | IN2019-123 |
| Volume (vol) | vol.119 |
| Number (no) | no.461 |
| Page | pp.267-272 |
| #Pages | 6 |
| Date of Issue | 2020-02-27 (IN) |
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