Paper Abstract and Keywords |
Presentation |
2020-06-18 14:00
Optimal Design for Level-Shifter-Less Approach using Channel Length Modulation & Body Biasing Tatsuya Watanabe, Usami Kimiyoshi (SIT) CAS2020-8 VLD2020-8 SIP2020-24 MSS2020-8 |
Abstract |
(in Japanese) |
(See Japanese page) |
(in English) |
A multi-VDD design realizes LSIs to be low power by allowing to use multiple different power supply voltages. In this design, conversion of the voltage amplitude of the signal is necessary. This is usually done by inserting a circuit called a level shifter, between voltage domains as an interface. However, insertion of level shifter has disadvantages in silicon footprint, power consumption, and delays. In this paper, we propose a level-shifter-less approach by increasing channel length. We also propose the optimal design using both channel length modulation and body biasing. |
Keyword |
(in Japanese) |
(See Japanese page) |
(in English) |
Level-Shifter-Less / Body Biasing / Channel Length Modulation / / / / / |
Reference Info. |
IEICE Tech. Rep., vol. 120, no. 66, VLD2020-8, pp. 41-46, June 2020. |
Paper # |
VLD2020-8 |
Date of Issue |
2020-06-11 (CAS, VLD, SIP, MSS) |
ISSN |
Online edition: ISSN 2432-6380 |
Copyright and reproduction |
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034) |
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CAS2020-8 VLD2020-8 SIP2020-24 MSS2020-8 |
Conference Information |
Committee |
MSS CAS SIP VLD |
Conference Date |
2020-06-18 - 2020-06-18 |
Place (in Japanese) |
(See Japanese page) |
Place (in English) |
Online |
Topics (in Japanese) |
(See Japanese page) |
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Paper Information |
Registration To |
VLD |
Conference Code |
2020-06-MSS-CAS-SIP-VLD |
Language |
Japanese |
Title (in Japanese) |
(See Japanese page) |
Sub Title (in Japanese) |
(See Japanese page) |
Title (in English) |
Optimal Design for Level-Shifter-Less Approach using Channel Length Modulation & Body Biasing |
Sub Title (in English) |
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Keyword(1) |
Level-Shifter-Less |
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Body Biasing |
Keyword(3) |
Channel Length Modulation |
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1st Author's Name |
Tatsuya Watanabe |
1st Author's Affiliation |
Shibaura Institute of Technology (SIT) |
2nd Author's Name |
Usami Kimiyoshi |
2nd Author's Affiliation |
Shibaura Institute of Technology (SIT) |
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Speaker |
Author-1 |
Date Time |
2020-06-18 14:00:00 |
Presentation Time |
25 minutes |
Registration for |
VLD |
Paper # |
CAS2020-8, VLD2020-8, SIP2020-24, MSS2020-8 |
Volume (vol) |
vol.120 |
Number (no) |
no.65(CAS), no.66(VLD), no.67(SIP), no.68(MSS) |
Page |
pp.41-46 |
#Pages |
6 |
Date of Issue |
2020-06-11 (CAS, VLD, SIP, MSS) |
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