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| Presentation | 2020-07-31 15:45 A Multiple Target Test Generation Method for Gate-Exhaustive Faults to Reduce the number of Test Patterns Ryuki Asami, Toshinori Hosokawa (Nihon Univ.), Masayoshi Yoshimura (Kyoto Sangyo Univ.), Masayuki Arai (Nihon Univ.)  CPSY2020-12 DC2020-12 |
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| Abstract | (in Japanese) | (See Japanese page) |
| (in English) | In recent years, as the high density and complexity of integrated circuits have increased, defects in cells have increased, and test generation methods for fault models in cells and test generation methods for gate-exhaustive fault models have been proposed. Since the number of gate-exhaustive faults is defined as the total sum of 2 to the power of the number of cell inputs, the number of faults and the number of test patterns drastically increase compared to the stuck-at fault model. In this paper, to reduce the number of test patterns, we propose a multiple target test generation method that enables detection of as many gate-exhaustive faults as possible with one test pattern during test generation. The proposed method was able to detect all detectable gate-exhaustive faults and to reduce the number of test patterns by 19 to 48% compared to the conventional method. | |
| Keyword | (in Japanese) | (See Japanese page) |
| (in English) | gate-exhaustive faults / multiple target fault test generation / test compaction / independent fault sets / Partial MaxSAT / / / | |
| Reference Info. | IEICE Tech. Rep., vol. 120, no. 122, DC2020-12, pp. 75-80, July 2020. | |
| Paper # | DC2020-12 | |
| Date of Issue | 2020-07-23 (CPSY, DC) | |
| ISSN | Online edition: ISSN 2432-6380 | |
| Copyright and reproduction |
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034) | |
| Download PDF | CPSY2020-12 DC2020-12 |
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| Conference Information | |
| Committee | CPSY DC IPSJ-ARC |
| Conference Date | 2020-07-30 - 2020-07-31 |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | Online |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | SWoPP2020: Parallel, Distributed and Cooperative Processing Systems and Dependable Computing |
| Paper Information | |
| Registration To | DC |
| Conference Code | 2020-07-CPSY-DC-ARC |
| Language | Japanese |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | A Multiple Target Test Generation Method for Gate-Exhaustive Faults to Reduce the number of Test Patterns |
| Sub Title (in English) | |
| Keyword(1) | gate-exhaustive faults |
| Keyword(2) | multiple target fault test generation |
| Keyword(3) | test compaction |
| Keyword(4) | independent fault sets |
| Keyword(5) | Partial MaxSAT |
| Keyword(6) | |
| Keyword(7) | |
| Keyword(8) | |
| 1st Author's Name | Ryuki Asami |
| 1st Author's Affiliation | Nihon University (Nihon Univ.) |
| 2nd Author's Name | Toshinori Hosokawa |
| 2nd Author's Affiliation | Nihon University (Nihon Univ.) |
| 3rd Author's Name | Masayoshi Yoshimura |
| 3rd Author's Affiliation | Kyoto Sangyo University (Kyoto Sangyo Univ.) |
| 4th Author's Name | Masayuki Arai |
| 4th Author's Affiliation | Nihon University (Nihon Univ.) |
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| Speaker | Author-1 |
| Date Time | 2020-07-31 15:45:00 |
| Presentation Time | 30 minutes |
| Registration for | DC |
| Paper # | CPSY2020-12, DC2020-12 |
| Volume (vol) | vol.120 |
| Number (no) | no.121(CPSY), no.122(DC) |
| Page | pp.75-80 |
| #Pages | 6 |
| Date of Issue | 2020-07-23 (CPSY, DC) |
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