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Presentation 2020-08-06 13:50
Over-the-top Si Interposer Embedding Backside Buried Metal to Reduce Power Supply Impedance
Takuji Miki, Makoto Nagata, Akihiro Tsukioka (Kobe Univ.), Noriyuki Miura (Osaka Univ.), Takaaki Okidono (ECSEC), Yuuki Araga, Naoya Watanabe, Haruo Shimamoto, Katsuya Kikuchi (AIST) SDM2020-5 ICD2020-5 Link to ES Tech. Rep. Archives: SDM2020-5 ICD2020-5
Abstract (in Japanese) (See Japanese page) 
(in English) A 2.5D structure with a Si interposer stacked on a CMOS chip is developed to reduce power supply impedance. A backside buried metal (BBM) in Si interposer provides low resistive wiring of power / ground nodes and also forms a large parasitic bypass capacitance between power and ground patterns, which drastically suppresses the power supply noise. The Si interposer was implemented over a cryptographic chip with a large scale digital circuit fabricated in 130 nm CMOS. The measured resistance values of power and ground line were reduced by 30% and 56%, respectively, and the measured bypass capacitance was increased by 2.4 nF, owing to the additional low resistive wiring in parallel and a large parasitic capacitance of the Si interposer and the stacking structure itself. An internal noise monitoring circuit embedded in the CMOS chip indicates that the proposed over-the-top Si interposer reduces a peak-to-peak power supply noise and DC drop during cryptographic operation to less than 50%.
Keyword (in Japanese) (See Japanese page) 
(in English) 2.5D implementation / Si interposer / Power supply impedance / Cryptographic circuit / / / /  
Reference Info. IEICE Tech. Rep., vol. 120, no. 127, ICD2020-5, pp. 19-24, Aug. 2020.
Paper # ICD2020-5 
Date of Issue 2020-07-30 (SDM, ICD) 
ISSN Online edition: ISSN 2432-6380
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All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034)
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Conference Information
Committee ICD SDM ITE-IST  
Conference Date 2020-08-06 - 2020-08-07 
Place (in Japanese) (See Japanese page) 
Place (in English) Online 
Topics (in Japanese) (See Japanese page) 
Topics (in English) Analog, Mixed Analog and Digital, RF, and Sensor Interface, Low Voltage/Low Power Techniques, Novel Devices/Circuits, and the Applications 
Paper Information
Registration To ICD 
Conference Code 2020-08-ICD-SDM-IST 
Language Japanese 
Title (in Japanese) (See Japanese page) 
Sub Title (in Japanese) (See Japanese page) 
Title (in English) Over-the-top Si Interposer Embedding Backside Buried Metal to Reduce Power Supply Impedance 
Sub Title (in English)  
Keyword(1) 2.5D implementation  
Keyword(2) Si interposer  
Keyword(3) Power supply impedance  
Keyword(4) Cryptographic circuit  
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1st Author's Name Takuji Miki  
1st Author's Affiliation Kobe University (Kobe Univ.)
2nd Author's Name Makoto Nagata  
2nd Author's Affiliation Kobe University (Kobe Univ.)
3rd Author's Name Akihiro Tsukioka  
3rd Author's Affiliation Kobe University (Kobe Univ.)
4th Author's Name Noriyuki Miura  
4th Author's Affiliation Osaka University (Osaka Univ.)
5th Author's Name Takaaki Okidono  
5th Author's Affiliation ECSEC (ECSEC)
6th Author's Name Yuuki Araga  
6th Author's Affiliation AIST (AIST)
7th Author's Name Naoya Watanabe  
7th Author's Affiliation AIST (AIST)
8th Author's Name Haruo Shimamoto  
8th Author's Affiliation AIST (AIST)
9th Author's Name Katsuya Kikuchi  
9th Author's Affiliation AIST (AIST)
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Speaker Author-1 
Date Time 2020-08-06 13:50:00 
Presentation Time 25 minutes 
Registration for ICD 
Paper # SDM2020-5, ICD2020-5 
Volume (vol) vol.120 
Number (no) no.126(SDM), no.127(ICD) 
Page pp.19-24 
#Pages
Date of Issue 2020-07-30 (SDM, ICD) 


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