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| Presentation | 2020-10-26 15:45 Low-Latency Countermeasure Circuit Oriented Hardware Trojan and its Evaluation Shu Takemoto, Yoshiya Ikezaki, Yusuke Nozaki, Masaya Yoshikawa (Meijo Univ.)  HWS2020-37 ICD2020-26 Link to ES Tech. Rep. Archives: ICD2020-26 |
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| Abstract | (in Japanese) | (See Japanese page) |
| (in English) | Outsourcing and the use of IP are the mainstream in the design and manufacturing of system LSIs. On the other hand, the threat of hardware trojans has been reported. When inserted in a security device, the security is greatly reduced by the behavior of the hardware trojan. Therefore, it is important to evaluate the hardware trojan for security devices. For this reason, this study evaluates hardware trojan insertion methods for low-latency lightweight cryptography. Specifically, a hardware trojan focusing on plaintext is inserted into the lightweight cryptographic PRINCE that implements a power analysis attack countermeasure circuit. Experiments evaluated the threat of inserted hardware trojans in terms of circuit size, power consumption and tamper resistance. | |
| Keyword | (in Japanese) | (See Japanese page) |
| (in English) | hardware security / hardware trojan / lightweight block cipher / power analysis attack / / / / | |
| Reference Info. | IEICE Tech. Rep., vol. 120, no. 211, HWS2020-37, pp. 71-76, Oct. 2020. | |
| Paper # | HWS2020-37 | |
| Date of Issue | 2020-10-19 (HWS, ICD) | |
| ISSN | Online edition: ISSN 2432-6380 | |
| Copyright and reproduction |
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034) | |
| Download PDF | HWS2020-37 ICD2020-26 Link to ES Tech. Rep. Archives: ICD2020-26 |
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| Conference Information | |
| Committee | ICD HWS |
| Conference Date | 2020-10-26 - 2020-10-26 |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | Online |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | Hardware Security, etc. |
| Paper Information | |
| Registration To | HWS |
| Conference Code | 2020-10-ICD-HWS |
| Language | Japanese |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | Low-Latency Countermeasure Circuit Oriented Hardware Trojan and its Evaluation |
| Sub Title (in English) | |
| Keyword(1) | hardware security |
| Keyword(2) | hardware trojan |
| Keyword(3) | lightweight block cipher |
| Keyword(4) | power analysis attack |
| Keyword(5) | |
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| 1st Author's Name | Shu Takemoto |
| 1st Author's Affiliation | Meijo University (Meijo Univ.) |
| 2nd Author's Name | Yoshiya Ikezaki |
| 2nd Author's Affiliation | Meijo University (Meijo Univ.) |
| 3rd Author's Name | Yusuke Nozaki |
| 3rd Author's Affiliation | Meijo University (Meijo Univ.) |
| 4th Author's Name | Masaya Yoshikawa |
| 4th Author's Affiliation | Meijo University (Meijo Univ.) |
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| Speaker | Author-1 |
| Date Time | 2020-10-26 15:45:00 |
| Presentation Time | 25 minutes |
| Registration for | HWS |
| Paper # | HWS2020-37, ICD2020-26 |
| Volume (vol) | vol.120 |
| Number (no) | no.211(HWS), no.212(ICD) |
| Page | pp.71-76 |
| #Pages | 6 |
| Date of Issue | 2020-10-19 (HWS, ICD) |
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