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Paper Abstract and Keywords
Presentation 2021-01-25 16:20
Residual signed-digit number - residual binary number conversion algorithm
Yuki Saba, Yuuki Tanaka, Shugang Wei (Gunma Univ.) VLD2020-51 CPSY2020-34 RECONF2020-70
Abstract (in Japanese) (See Japanese page) 
(in English) By applying SD(Signed-Digit) number representation, redundant residue number representation including negative number can be used
and high-speed residue arithmetic operation is realized. However, since ordinary modulo operations don't handle negative numbers,
it is necessary to convert the residue SD numbers that have become negative numbers to positive numbers in order to treat
them as modulo binary numbers. In this paper, we propose algorithms to convert the number with SD number representation to the residue
binary numbers on moduli $2^n,2^n-1$ and $2^n+1$. We have designed the
conversion circuits with VHDL by using a $0.18{rm mu m}$ CMOS gate array technology library.
Keyword (in Japanese) (See Japanese page) 
(in English) SD(Signed-Digit) number / residue SD number / residue binary number / / / / /  
Reference Info. IEICE Tech. Rep., vol. 120, no. 337, VLD2020-51, pp. 69-74, Jan. 2021.
Paper # VLD2020-51 
Date of Issue 2021-01-18 (VLD, CPSY, RECONF) 
ISSN Print edition: ISSN 0913-5685  Online edition: ISSN 2432-6380
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034)
Download PDF VLD2020-51 CPSY2020-34 RECONF2020-70

Conference Information
Conference Date 2021-01-25 - 2021-01-26 
Place (in Japanese) (See Japanese page) 
Place (in English) Online 
Topics (in Japanese) (See Japanese page) 
Topics (in English) FPGA Applications, etc. 
Paper Information
Registration To VLD 
Conference Code 2021-01-CPSY-RECONF-VLD-ARC-SLDM 
Language Japanese 
Title (in Japanese) (See Japanese page) 
Sub Title (in Japanese) (See Japanese page) 
Title (in English) Residual signed-digit number - residual binary number conversion algorithm 
Sub Title (in English)  
Keyword(1) SD(Signed-Digit) number  
Keyword(2) residue SD number  
Keyword(3) residue binary number  
1st Author's Name Yuki Saba  
1st Author's Affiliation Gunma University (Gunma Univ.)
2nd Author's Name Yuuki Tanaka  
2nd Author's Affiliation Gunma University (Gunma Univ.)
3rd Author's Name Shugang Wei  
3rd Author's Affiliation Gunma University (Gunma Univ.)
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Speaker Author-1 
Date Time 2021-01-25 16:20:00 
Presentation Time 25 minutes 
Registration for VLD 
Paper # VLD2020-51, CPSY2020-34, RECONF2020-70 
Volume (vol) vol.120 
Number (no) no.337(VLD), no.338(CPSY), no.339(RECONF) 
Page pp.69-74 
Date of Issue 2021-01-18 (VLD, CPSY, RECONF) 

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