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| Paper Abstract and Keywords | ||
| Presentation | 2021-01-26 09:25 FPGA Accelerator Design for Real-Time Object Detection Koichiro Ban, Masanori Furuta, Daisuke Kobayashi (Toshiba)  VLD2020-56 CPSY2020-39 RECONF2020-75 |
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| Abstract | (in Japanese) | (See Japanese page) |
| (in English) | This paper presents a FPGA accelerator design for a real-time object detection algorithm using MASSD (Multi-Scale Attention SSD), which incorporates a self-attention mechanism in SSD (Single Shot Detector).The FPGA accelerator employs dynamic quantization method to decrease resource utilization while maintaining computational accuracy. Autonomous data transfer mechanism in the accelerator increases the utilization of the computational unit by reducing DRAM access. The developed FPGA system successfully operates at 10 FPS with 512x512 input images. | |
| Keyword | (in Japanese) | (See Japanese page) |
| (in English) | Accelerator / Object Detection / SSD / Attention / MASSD / / / | |
| Reference Info. | IEICE Tech. Rep., vol. 120, no. 339, RECONF2020-75, pp. 96-100, Jan. 2021. | |
| Paper # | RECONF2020-75 | |
| Date of Issue | 2021-01-18 (VLD, CPSY, RECONF) | |
| ISSN | Online edition: ISSN 2432-6380 | |
| Copyright and reproduction |
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034) | |
| Download PDF | VLD2020-56 CPSY2020-39 RECONF2020-75 |
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| Conference Information | |
| Committee | CPSY RECONF VLD IPSJ-ARC IPSJ-SLDM |
| Conference Date | 2021-01-25 - 2021-01-26 |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | Online |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | FPGA Applications, etc. |
| Paper Information | |
| Registration To | RECONF |
| Conference Code | 2021-01-CPSY-RECONF-VLD-ARC-SLDM |
| Language | Japanese |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | FPGA Accelerator Design for Real-Time Object Detection |
| Sub Title (in English) | |
| Keyword(1) | Accelerator |
| Keyword(2) | Object Detection |
| Keyword(3) | SSD |
| Keyword(4) | Attention |
| Keyword(5) | MASSD |
| Keyword(6) | |
| Keyword(7) | |
| Keyword(8) | |
| 1st Author's Name | Koichiro Ban |
| 1st Author's Affiliation | Toshiba Corporation (Toshiba) |
| 2nd Author's Name | Masanori Furuta |
| 2nd Author's Affiliation | Toshiba Corporation (Toshiba) |
| 3rd Author's Name | Daisuke Kobayashi |
| 3rd Author's Affiliation | Toshiba Corporation (Toshiba) |
| 4th Author's Name | |
| 4th Author's Affiliation | () |
| 5th Author's Name | |
| 5th Author's Affiliation | () |
| 6th Author's Name | |
| 6th Author's Affiliation | () |
| Speaker | Author-1 |
| Date Time | 2021-01-26 09:25:00 |
| Presentation Time | 25 minutes |
| Registration for | RECONF |
| Paper # | VLD2020-56, CPSY2020-39, RECONF2020-75 |
| Volume (vol) | vol.120 |
| Number (no) | no.337(VLD), no.338(CPSY), no.339(RECONF) |
| Page | pp.96-100 |
| #Pages | 5 |
| Date of Issue | 2021-01-18 (VLD, CPSY, RECONF) |
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