Paper Abstract and Keywords |
Presentation |
2021-04-12 10:50
Performance Evaluation of an FPGA-Based Pairing Computation Accelerator Junichi Sakamoto, Naoki Yoshida, Tsutomu Matsumoto (YNU) HWS2021-3 |
Abstract |
(in Japanese) |
(See Japanese page) |
(in English) |
Several hardware-based accelerators have been proposed to speed up or reduce the power consumption of computationally expensive pairing calculations. In most previous studies, only the performance of the pairing-calculation circuit was evaluated. However, in practical use, the performance, including the interface part, is required. We added a PCIe interface to the fastest FPGA implementation of the pairing calculation and evaluated its performance, including the interface. The results show that the FPGA implementation of the pairing calculation is superior to the fastest software implementation in terms of computation time (62.5%) and energy consumption (49%), even after taking into account the overhead of API processing and communication interfaces. |
Keyword |
(in Japanese) |
(See Japanese page) |
(in English) |
pairing / BN254 / PCIe / / / / / |
Reference Info. |
IEICE Tech. Rep., vol. 121, no. 1, HWS2021-3, pp. 13-18, April 2021. |
Paper # |
HWS2021-3 |
Date of Issue |
2021-04-05 (HWS) |
ISSN |
Online edition: ISSN 2432-6380 |
Copyright and reproduction |
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034) |
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HWS2021-3 |
Conference Information |
Committee |
HWS |
Conference Date |
2021-04-12 - 2021-04-12 |
Place (in Japanese) |
(See Japanese page) |
Place (in English) |
Tokyo University/Online |
Topics (in Japanese) |
(See Japanese page) |
Topics (in English) |
Hardware Security |
Paper Information |
Registration To |
HWS |
Conference Code |
2021-04-HWS |
Language |
Japanese |
Title (in Japanese) |
(See Japanese page) |
Sub Title (in Japanese) |
(See Japanese page) |
Title (in English) |
Performance Evaluation of an FPGA-Based Pairing Computation Accelerator |
Sub Title (in English) |
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pairing |
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BN254 |
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PCIe |
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1st Author's Name |
Junichi Sakamoto |
1st Author's Affiliation |
Yokohama National University (YNU) |
2nd Author's Name |
Naoki Yoshida |
2nd Author's Affiliation |
Yokohama National University (YNU) |
3rd Author's Name |
Tsutomu Matsumoto |
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Yokohama National University (YNU) |
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Speaker |
Author-1 |
Date Time |
2021-04-12 10:50:00 |
Presentation Time |
25 minutes |
Registration for |
HWS |
Paper # |
HWS2021-3 |
Volume (vol) |
vol.121 |
Number (no) |
no.1 |
Page |
pp.13-18 |
#Pages |
6 |
Date of Issue |
2021-04-05 (HWS) |
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