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Paper Abstract and Keywords
Presentation 2022-03-01 14:20
Evaluation of Efficiency for a Method to Locate High Power Consumption with Switching Provability
Ryu Hoshino, Taiki Utsunomiya, Kohei Miyase, Xiaoqing Wen, Seiji Kajihara (Kyutech) DC2021-73
Abstract (in Japanese) (See Japanese page) 
(in English) In recent years, as the high speed and miniaturization of LSIs have improved, it has become more difficult to test LSIs.During LSI testing, the power consumption increases due to more switching activities than in normal operation, and then excessive IR-drop occurs. When excessive IR-drop occurs, excessive delays which may lead to test malfunction even if circuits with no problems in normal operation Therefore, in order to avoid test malfunction, it is necessary to apply appropriate techniques before LSI testing is conducted. Excessive IR-drop does not occur in the entire circuit, but in areas where switching activities are densely concentrated.Therefore, in order to effectively reduce excessive IR-drops, it is important to locate areas where switching activity densely occurs.In this paper, we present the method to locate areas where many switching activities occur with switching probabilities of logic gates, and then we evaluate its effectiveness and efficiency.
Keyword (in Japanese) (See Japanese page) 
(in English) At-speed testing / test power / transition delay test / IR-drop / test malfunction / / /  
Reference Info. IEICE Tech. Rep., vol. 121, no. 388, DC2021-73, pp. 51-56, March 2022.
Paper # DC2021-73 
Date of Issue 2022-02-22 (DC) 
ISSN Online edition: ISSN 2432-6380
Copyright
and
reproduction
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034)
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Conference Information
Committee DC  
Conference Date 2022-03-01 - 2022-03-01 
Place (in Japanese) (See Japanese page) 
Place (in English) Kikai-Shinko-Kaikan Bldg. 
Topics (in Japanese) (See Japanese page) 
Topics (in English)  
Paper Information
Registration To DC 
Conference Code 2022-03-DC 
Language Japanese 
Title (in Japanese) (See Japanese page) 
Sub Title (in Japanese) (See Japanese page) 
Title (in English) Evaluation of Efficiency for a Method to Locate High Power Consumption with Switching Provability 
Sub Title (in English)  
Keyword(1) At-speed testing  
Keyword(2) test power  
Keyword(3) transition delay test  
Keyword(4) IR-drop  
Keyword(5) test malfunction  
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Keyword(8)  
1st Author's Name Ryu Hoshino  
1st Author's Affiliation Kyushu Institute of Technology (Kyutech)
2nd Author's Name Taiki Utsunomiya  
2nd Author's Affiliation Kyushu Institute of Technology (Kyutech)
3rd Author's Name Kohei Miyase  
3rd Author's Affiliation Kyushu Institute of Technology (Kyutech)
4th Author's Name Xiaoqing Wen  
4th Author's Affiliation Kyushu Institute of Technology (Kyutech)
5th Author's Name Seiji Kajihara  
5th Author's Affiliation Kyushu Institute of Technology (Kyutech)
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Speaker Author-1 
Date Time 2022-03-01 14:20:00 
Presentation Time 25 minutes 
Registration for DC 
Paper # DC2021-73 
Volume (vol) vol.121 
Number (no) no.388 
Page pp.51-56 
#Pages
Date of Issue 2022-02-22 (DC) 


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