Paper Abstract and Keywords |
Presentation |
2022-03-07 09:35
Bottleneck Channel Routing to Reduce the Area of Analog VLSI Kazuya Taniguchi, Satoshi Tayu, Atsushi Takahashi (Tokyo Tech), Yukichi Todoroki, Makoto Minami (Jedat) VLD2021-77 HWS2021-54 |
Abstract |
(in Japanese) |
(See Japanese page) |
(in English) |
Design automation that realizes analog integrated circuits to meet performance specifications in a small area is desired. In order to reduce the layout area, "Bottleneck Routing" is proposed in which two wires go through a routing track in bottleneck region. A two-layer routing problem that consists of the bottleneck channel and the adjacent regions where the HV rule is not applicable is defined. The proposed algorithm generates two-layer routing in which the number of intersections is minimized and the wire of a net includes at most one via, by using a U-shaped routing model. Physical routing can be obtained if algorithm generates a feasible topological routing. |
Keyword |
(in Japanese) |
(See Japanese page) |
(in English) |
2-layer Bottleneck Routing / Analog VLSI / / / / / / |
Reference Info. |
IEICE Tech. Rep., vol. 121, no. 412, VLD2021-77, pp. 7-12, March 2022. |
Paper # |
VLD2021-77 |
Date of Issue |
2022-02-28 (VLD, HWS) |
ISSN |
Online edition: ISSN 2432-6380 |
Copyright and reproduction |
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034) |
Download PDF |
VLD2021-77 HWS2021-54 |
Conference Information |
Committee |
VLD HWS |
Conference Date |
2022-03-07 - 2022-03-08 |
Place (in Japanese) |
(See Japanese page) |
Place (in English) |
Online |
Topics (in Japanese) |
(See Japanese page) |
Topics (in English) |
Design Technology for System-on-Silicon, Hardware Security, etc. |
Paper Information |
Registration To |
VLD |
Conference Code |
2022-03-VLD-HWS |
Language |
Japanese |
Title (in Japanese) |
(See Japanese page) |
Sub Title (in Japanese) |
(See Japanese page) |
Title (in English) |
Bottleneck Channel Routing to Reduce the Area of Analog VLSI |
Sub Title (in English) |
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Keyword(1) |
2-layer Bottleneck Routing |
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Analog VLSI |
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1st Author's Name |
Kazuya Taniguchi |
1st Author's Affiliation |
Tokyo Institute of Technology (Tokyo Tech) |
2nd Author's Name |
Satoshi Tayu |
2nd Author's Affiliation |
Tokyo Institute of Technology (Tokyo Tech) |
3rd Author's Name |
Atsushi Takahashi |
3rd Author's Affiliation |
Tokyo Institute of Technology (Tokyo Tech) |
4th Author's Name |
Yukichi Todoroki |
4th Author's Affiliation |
Jedat (Jedat) |
5th Author's Name |
Makoto Minami |
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Jedat (Jedat) |
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Speaker |
Author-1 |
Date Time |
2022-03-07 09:35:00 |
Presentation Time |
25 minutes |
Registration for |
VLD |
Paper # |
VLD2021-77, HWS2021-54 |
Volume (vol) |
vol.121 |
Number (no) |
no.412(VLD), no.413(HWS) |
Page |
pp.7-12 |
#Pages |
6 |
Date of Issue |
2022-02-28 (VLD, HWS) |
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