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| Presentation | 2022-03-08 11:25 A Method for Automatic Test Pattern Generation using an SMT Solver for HDL Code Ryoichi Isawa, Nobuyuki Kanaya, Yoshitada Fujiwara, Tatsuta Takehisa, Hayato Ushimaru, Dai Arisue, Daisuke Makita, Satoshi Mimura, Daisuke Inoue (NICT)  VLD2021-95 HWS2021-72 |
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| Abstract | (in Japanese) | (See Japanese page) |
| (in English) | (Not available yet) | |
| Keyword | (in Japanese) | (See Japanese page) |
| (in English) | Hardware Description Language / Branch coverage / Satisfiability modulo theories / FPGA / / / / | |
| Reference Info. | IEICE Tech. Rep., vol. 121, no. 413, HWS2021-72, pp. 105-110, March 2022. | |
| Paper # | HWS2021-72 | |
| Date of Issue | 2022-02-28 (VLD, HWS) | |
| ISSN | Online edition: ISSN 2432-6380 | |
| Copyright and reproduction |
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034) | |
| Download PDF | VLD2021-95 HWS2021-72 |
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| Conference Information | |
| Committee | VLD HWS |
| Conference Date | 2022-03-07 - 2022-03-08 |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | Online |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | Design Technology for System-on-Silicon, Hardware Security, etc. |
| Paper Information | |
| Registration To | HWS |
| Conference Code | 2022-03-VLD-HWS |
| Language | Japanese |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | A Method for Automatic Test Pattern Generation using an SMT Solver for HDL Code |
| Sub Title (in English) | |
| Keyword(1) | Hardware Description Language |
| Keyword(2) | Branch coverage |
| Keyword(3) | Satisfiability modulo theories |
| Keyword(4) | FPGA |
| Keyword(5) | |
| Keyword(6) | |
| Keyword(7) | |
| Keyword(8) | |
| 1st Author's Name | Ryoichi Isawa |
| 1st Author's Affiliation | National Institute of Information and Communications Technology (NICT) |
| 2nd Author's Name | Nobuyuki Kanaya |
| 2nd Author's Affiliation | National Institute of Information and Communications Technology (NICT) |
| 3rd Author's Name | Yoshitada Fujiwara |
| 3rd Author's Affiliation | National Institute of Information and Communications Technology (NICT) |
| 4th Author's Name | Tatsuta Takehisa |
| 4th Author's Affiliation | National Institute of Information and Communications Technology (NICT) |
| 5th Author's Name | Hayato Ushimaru |
| 5th Author's Affiliation | National Institute of Information and Communications Technology (NICT) |
| 6th Author's Name | Dai Arisue |
| 6th Author's Affiliation | National Institute of Information and Communications Technology (NICT) |
| 7th Author's Name | Daisuke Makita |
| 7th Author's Affiliation | National Institute of Information and Communications Technology (NICT) |
| 8th Author's Name | Satoshi Mimura |
| 8th Author's Affiliation | National Institute of Information and Communications Technology (NICT) |
| 9th Author's Name | Daisuke Inoue |
| 9th Author's Affiliation | National Institute of Information and Communications Technology (NICT) |
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| Speaker | Author-1 |
| Date Time | 2022-03-08 11:25:00 |
| Presentation Time | 25 minutes |
| Registration for | HWS |
| Paper # | VLD2021-95, HWS2021-72 |
| Volume (vol) | vol.121 |
| Number (no) | no.412(VLD), no.413(HWS) |
| Page | pp.105-110 |
| #Pages | 6 |
| Date of Issue | 2022-02-28 (VLD, HWS) |
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