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Paper Abstract and Keywords
Presentation 2022-03-11 14:10
Imprecise Mixed Criticality Scheduling for SMT Processor
Reo Nagura, Nobuyuki Yamasaki (Keio Univ.) CPSY2021-63 DC2021-97
Abstract (in Japanese) (See Japanese page) 
(in English) Recently, in the field of real-time scheduling, scheduling methods for mixed-criticality (MC) systems, in which tasks of different criticality are mixed, have been studied. In an MC system, if a high-criticality task does not complete its execution even after the expected execution time, the system mode switches to emergency mode, then low-criticality tasks are dropped for high-criticality tasks. On the other hand, scheduling methods for imprecise computation model, which divides tasks into mandatory parts and optional parts, have been studied. In the imprecise computation model, when the system is overloaded, it is possible to maintain a minimum execution quality by giving high priority to the mandatory part of the task. In this study, we propose the Imprecise Mixed Criticality (IMC) system, which combines the above two methods. In the IMC system, the system is able to maintain the minimum quality of execution even in emergency or overload situations.
Keyword (in Japanese) (See Japanese page) 
(in English) Real-Time System / Processor Scheduling / / / / / /  
Reference Info. IEICE Tech. Rep., vol. 121, no. 425, CPSY2021-63, pp. 109-114, March 2022.
Paper # CPSY2021-63 
Date of Issue 2022-03-03 (CPSY, DC) 
ISSN Online edition: ISSN 2432-6380
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Conference Information
Committee CPSY DC IPSJ-SLDM IPSJ-EMB IPSJ-ARC  
Conference Date 2022-03-10 - 2022-03-11 
Place (in Japanese) (See Japanese page) 
Place (in English) Online 
Topics (in Japanese) (See Japanese page) 
Topics (in English) ETNET2021 
Paper Information
Registration To CPSY 
Conference Code 2022-03-CPSY-DC-SLDM-EMB-ARC 
Language Japanese 
Title (in Japanese) (See Japanese page) 
Sub Title (in Japanese) (See Japanese page) 
Title (in English) Imprecise Mixed Criticality Scheduling for SMT Processor 
Sub Title (in English)  
Keyword(1) Real-Time System  
Keyword(2) Processor Scheduling  
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1st Author's Name Reo Nagura  
1st Author's Affiliation Keio University (Keio Univ.)
2nd Author's Name Nobuyuki Yamasaki  
2nd Author's Affiliation Keio University (Keio Univ.)
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Speaker Author-1 
Date Time 2022-03-11 14:10:00 
Presentation Time 20 minutes 
Registration for CPSY 
Paper # CPSY2021-63, DC2021-97 
Volume (vol) vol.121 
Number (no) no.425(CPSY), no.426(DC) 
Page pp.109-114 
#Pages
Date of Issue 2022-03-03 (CPSY, DC) 


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