Paper Abstract and Keywords |
Presentation |
2022-06-29 14:20
LSI implementation of analog CMOS majority circuit for neural network applications Satoshi Ono, Satoshi Moriya, Yuka Kanke, Hideaki Yamamoto (Tohoku Univ.), Yasushi Yuminaka (Gunma Univ.), Shigeo Sato (Tohoku Univ.) NC2022-27 IBISML2022-27 |
Abstract |
(in Japanese) |
(See Japanese page) |
(in English) |
Majority logic circuit is a circuit whose output is the majority value of multiple binary inputs. It can be applied to binarized neural networks and reservoir computing. When majority logic is implemented in analog circuits, only about 4N transistors are needed for N inputs, and thus the circuit area is significantly reduced in comparison to a digital circuit implementation. In this study, we implemented analog majority logic circuits using 0.18 µm CMOS technology. We measured the circuits with N = 11 and 101 and confirmed that they properly operated. |
Keyword |
(in Japanese) |
(See Japanese page) |
(in English) |
Majority logic / Analog circuit implementation / Neural Network / / / / / |
Reference Info. |
IEICE Tech. Rep., vol. 122, no. 89, NC2022-27, pp. 189-192, June 2022. |
Paper # |
NC2022-27 |
Date of Issue |
2022-06-20 (NC, IBISML) |
ISSN |
Online edition: ISSN 2432-6380 |
Copyright and reproduction |
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034) |
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NC2022-27 IBISML2022-27 |
Conference Information |
Committee |
NC IBISML IPSJ-BIO IPSJ-MPS |
Conference Date |
2022-06-27 - 2022-06-29 |
Place (in Japanese) |
(See Japanese page) |
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Topics (in Japanese) |
(See Japanese page) |
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Paper Information |
Registration To |
NC |
Conference Code |
2022-06-NC-IBISML-BIO-MPS |
Language |
Japanese |
Title (in Japanese) |
(See Japanese page) |
Sub Title (in Japanese) |
(See Japanese page) |
Title (in English) |
LSI implementation of analog CMOS majority circuit for neural network applications |
Sub Title (in English) |
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Keyword(1) |
Majority logic |
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Analog circuit implementation |
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Neural Network |
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1st Author's Name |
Satoshi Ono |
1st Author's Affiliation |
Tohoku University (Tohoku Univ.) |
2nd Author's Name |
Satoshi Moriya |
2nd Author's Affiliation |
Tohoku University (Tohoku Univ.) |
3rd Author's Name |
Yuka Kanke |
3rd Author's Affiliation |
Tohoku University (Tohoku Univ.) |
4th Author's Name |
Hideaki Yamamoto |
4th Author's Affiliation |
Tohoku University (Tohoku Univ.) |
5th Author's Name |
Yasushi Yuminaka |
5th Author's Affiliation |
Gunma University (Gunma Univ.) |
6th Author's Name |
Shigeo Sato |
6th Author's Affiliation |
Tohoku University (Tohoku Univ.) |
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Speaker |
Author-1 |
Date Time |
2022-06-29 14:20:00 |
Presentation Time |
25 minutes |
Registration for |
NC |
Paper # |
NC2022-27, IBISML2022-27 |
Volume (vol) |
vol.122 |
Number (no) |
no.89(NC), no.90(IBISML) |
Page |
pp.189-192 |
#Pages |
4 |
Date of Issue |
2022-06-20 (NC, IBISML) |
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