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Paper Abstract and Keywords
Presentation 2022-07-28 13:30
Preliminary evaluation of "SLMLET" chip with RISC-V MP and SLM reconfigurable logic
Yosuke Yanai (Keio Univ.), Takuya Kojima (Tokyo Univ.), Hayate Okuhara (NUS.), Hideharu Amano (Keio Univ.), Masahiro Iida (Kumamoto Univ.) CPSY2022-8 DC2022-8
Abstract (in Japanese) (See Japanese page) 
(in English) In recent years, processing power in IoT edge devices has been further improved. Therefore, a solution called a mixed FPGA/CPU SoC has been attracting attention. Instead of the conventional high-end mixed SoC with large area and power consumption, a compact and low-power mixed SoC combining a relatively small microprocessor and an embedded FPGA IP, eFPGA (Embedded FPGA), has already been discussed as an effective solution.
Based on this, we are developing SLMLET, a new compact and low-power SoC for IoT edge devices that combines SLM (Scalable Logic Module) reconfigurable logic developed by Kumamoto University, RISC-V CPU, SRAM, and external I/F. SLM has a small amount of bitstream size and small logic cells, and RISC-V CPUs are characterized by their small size and the existence of many open-source implementations.
This paper introduces the SLMLET chip and evaluates the DMA transfer performance between SLMLETs using Hyperbus, a high-speed interface between the chips, as a pre-production evaluation. The results showed that when the Hyperbus controller was operated at 50 MHz, which is the assumed speed for logic synthesis, transfers of 1024 bytes or more exceeded 90% of the maximum bandwidth, and transfers of 65535 bytes, the maximum size supported by the controller, exceeded 99.9% of the maximum bandwidth, 799.4Mbps was confirmed to be achievable.
Keyword (in Japanese) (See Japanese page) 
(in English) RISC-V / eFPGA / SLM Reconfigurable Logic / Mixed SoC / / / /  
Reference Info. IEICE Tech. Rep., vol. 122, no. 133, CPSY2022-8, pp. 41-46, July 2022.
Paper # CPSY2022-8 
Date of Issue 2022-07-20 (CPSY, DC) 
ISSN Online edition: ISSN 2432-6380
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All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034)
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Conference Information
Committee CPSY DC IPSJ-ARC  
Conference Date 2022-07-27 - 2022-07-29 
Place (in Japanese) (See Japanese page) 
Place (in English) Kaikyo Messe Shimonoseki 
Topics (in Japanese) (See Japanese page) 
Topics (in English) SWoPP2022: Parallel, Distributed and Cooperative Processing Systems and Dependable Computing 
Paper Information
Registration To CPSY 
Conference Code 2022-07-CPSY-DC-ARC 
Language Japanese 
Title (in Japanese) (See Japanese page) 
Sub Title (in Japanese) (See Japanese page) 
Title (in English) Preliminary evaluation of "SLMLET" chip with RISC-V MP and SLM reconfigurable logic 
Sub Title (in English)  
Keyword(1) RISC-V  
Keyword(2) eFPGA  
Keyword(3) SLM Reconfigurable Logic  
Keyword(4) Mixed SoC  
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1st Author's Name Yosuke Yanai  
1st Author's Affiliation Keio University (Keio Univ.)
2nd Author's Name Takuya Kojima  
2nd Author's Affiliation Tokyo University (Tokyo Univ.)
3rd Author's Name Hayate Okuhara  
3rd Author's Affiliation National University of Singapore (NUS.)
4th Author's Name Hideharu Amano  
4th Author's Affiliation Keio University (Keio Univ.)
5th Author's Name Masahiro Iida  
5th Author's Affiliation Kumamoto University (Kumamoto Univ.)
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Speaker Author-1 
Date Time 2022-07-28 13:30:00 
Presentation Time 30 minutes 
Registration for CPSY 
Paper # CPSY2022-8, DC2022-8 
Volume (vol) vol.122 
Number (no) no.133(CPSY), no.134(DC) 
Page pp.41-46 
#Pages
Date of Issue 2022-07-20 (CPSY, DC) 


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