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Paper Abstract and Keywords
Presentation 2022-07-29 11:00
Efficient placement of coherence directories in memory networks
Yuki Kameyama, Naoya Niwa, Daichi Fujiki (Keio Univ.), Michihiro Koibuchi (NII), Hidearu Amano (Keio Univ.) CPSY2022-14 DC2022-14
Abstract (in Japanese) (See Japanese page) 
(in English) Memory Cube (MC) is a memory module that manages three-dimensional stacking of DRAM chips with a logic layer on the bottom layer. The logic layer has a routing function and can route packets to their destinations. Therefore, a Memory-centric Network (MCN) has been proposed to construct a memory network by interconnecting multiple MCs. However, the number of message hops and latency for coherence management are larger in MCNs than in conventional networks that directly connect processors. In conventional MCNs, the coherence directory, which manages data coherence, is assumed to be located in the processor. However, if the coherence directory is placed in the processor, when accessing an MC that is not managed by itself from the processor's point of view, it is necessary to access another processor to check the sharer information. This can be an overhead, especially for write accesses where invalidation signals and ACK communication occur. Therefore, we propose a method in which a coherence directory is placed in the logic layer of the MC and the MC manages the coherence of its own data. This eliminates the need to access other processors to check the sharer information and reduces the number of message hops and latency for coherence management. Evaluation with synthetic traffic and real applications showed that the proposed method can reduce the number of cycles by about 15% for synthetic traffic and by about 25% for real applications.
Keyword (in Japanese) (See Japanese page) 
(in English) Memory Cube / Memory Network / Coherence Directory / Memory-centric Network / HMC / / /  
Reference Info. IEICE Tech. Rep., vol. 122, no. 133, CPSY2022-14, pp. 77-82, July 2022.
Paper # CPSY2022-14 
Date of Issue 2022-07-20 (CPSY, DC) 
ISSN Online edition: ISSN 2432-6380
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Conference Information
Committee CPSY DC IPSJ-ARC  
Conference Date 2022-07-27 - 2022-07-29 
Place (in Japanese) (See Japanese page) 
Place (in English) Kaikyo Messe Shimonoseki 
Topics (in Japanese) (See Japanese page) 
Topics (in English) SWoPP2022: Parallel, Distributed and Cooperative Processing Systems and Dependable Computing 
Paper Information
Registration To CPSY 
Conference Code 2022-07-CPSY-DC-ARC 
Language Japanese 
Title (in Japanese) (See Japanese page) 
Sub Title (in Japanese) (See Japanese page) 
Title (in English) Efficient placement of coherence directories in memory networks 
Sub Title (in English)  
Keyword(1) Memory Cube  
Keyword(2) Memory Network  
Keyword(3) Coherence Directory  
Keyword(4) Memory-centric Network  
Keyword(5) HMC  
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1st Author's Name Yuki Kameyama  
1st Author's Affiliation Keio University (Keio Univ.)
2nd Author's Name Naoya Niwa  
2nd Author's Affiliation Keio University (Keio Univ.)
3rd Author's Name Daichi Fujiki  
3rd Author's Affiliation Keio University (Keio Univ.)
4th Author's Name Michihiro Koibuchi  
4th Author's Affiliation National Institute of Informatics (NII)
5th Author's Name Hidearu Amano  
5th Author's Affiliation Keio University (Keio Univ.)
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Speaker Author-1 
Date Time 2022-07-29 11:00:00 
Presentation Time 30 minutes 
Registration for CPSY 
Paper # CPSY2022-14, DC2022-14 
Volume (vol) vol.122 
Number (no) no.133(CPSY), no.134(DC) 
Page pp.77-82 
#Pages
Date of Issue 2022-07-20 (CPSY, DC) 


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