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Paper Abstract and Keywords
Presentation 2022-09-29 10:25
Analog circuit implementation of spiking neural networks and its application to time-series information processing
Satoshi Moriya, Hideaki Yamamoto (Tohoku Univ), Yasushi Yuminaka (Gunma Univ.), Shigeo Sato, Yoshihiko Horio (Tohoku Univ) NC2022-33
Abstract (in Japanese) (See Japanese page) 
(in English) Edge computing in which low-dimensional signals such as sensor output are processed nearby sensors have become increasingly important. Spiking neural networks (SNNs), which simulate the dynamics of neural circuits, have attracted attention as a suitable information processing technology for edge computing due to their efficiency to handle not only spatial information but also temporal information. In this study, we designed and fabricated neuron circuits and SNN circuits that reproduce neural spikes with low power consumption by taking advantage of the analog characteristics of CMOS transistors. We found that the complex neural spikes were reproduced with power consumption of less than 100 fJ/spike. We also applied the framework of reservoir computation to spike trains obtained from SNN circuits and showed that the proposed circuits can be applied to time series information processing. These results contribute to the realization of low-power edge devices.
Keyword (in Japanese) (See Japanese page) 
(in English) spiking neuron / spiking neural networks / analog circuit / / / / /  
Reference Info. IEICE Tech. Rep., vol. 122, no. 195, NC2022-33, pp. 5-5, Sept. 2022.
Paper # NC2022-33 
Date of Issue 2022-09-22 (NC) 
ISSN Online edition: ISSN 2432-6380
Copyright
and
reproduction
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034)
Download PDF NC2022-33

Conference Information
Committee NC MBE  
Conference Date 2022-09-29 - 2022-09-30 
Place (in Japanese) (See Japanese page) 
Place (in English) Tohoku Univ. 
Topics (in Japanese) (See Japanese page) 
Topics (in English) Brain Architecture, NC, ME 
Paper Information
Registration To NC 
Conference Code 2022-09-NC-MBE 
Language Japanese 
Title (in Japanese) (See Japanese page) 
Sub Title (in Japanese) (See Japanese page) 
Title (in English) Analog circuit implementation of spiking neural networks and its application to time-series information processing 
Sub Title (in English)  
Keyword(1) spiking neuron  
Keyword(2) spiking neural networks  
Keyword(3) analog circuit  
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1st Author's Name Satoshi Moriya  
1st Author's Affiliation Tohoku University (Tohoku Univ)
2nd Author's Name Hideaki Yamamoto  
2nd Author's Affiliation Tohoku University (Tohoku Univ)
3rd Author's Name Yasushi Yuminaka  
3rd Author's Affiliation Gunma University (Gunma Univ.)
4th Author's Name Shigeo Sato  
4th Author's Affiliation Tohoku University (Tohoku Univ)
5th Author's Name Yoshihiko Horio  
5th Author's Affiliation Tohoku University (Tohoku Univ)
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Speaker Author-1 
Date Time 2022-09-29 10:25:00 
Presentation Time 25 minutes 
Registration for NC 
Paper # NC2022-33 
Volume (vol) vol.122 
Number (no) no.195 
Page p.5 
#Pages
Date of Issue 2022-09-22 (NC) 


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